clk/zynq/pll: Fix documentation for PLL register function
authorSoren Brinkmann <soren.brinkmann@xilinx.com>
Fri, 19 Jul 2013 17:16:44 +0000 (10:16 -0700)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 20 Aug 2013 05:54:40 +0000 (07:54 +0200)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/clk/zynq/pll.c

index 47e307c25a7b0703170be22449674677dce54eec..6daa7b6702ed91219ea4a332ba6dbb32f9ad7598 100644 (file)
@@ -182,7 +182,13 @@ static const struct clk_ops zynq_pll_ops = {
 
 /**
  * clk_register_zynq_pll() - Register PLL with the clock framework
- * @np Pointer to the DT device node
+ * @name       PLL name
+ * @parent     Parent clock name
+ * @pll_ctrl   Pointer to PLL control register
+ * @pll_status Pointer to PLL status register
+ * @lock_index Bit index to this PLL's lock status bit in @pll_status
+ * @lock       Register lock
+ * Returns handle to the registered clock.
  */
 struct clk *clk_register_zynq_pll(const char *name, const char *parent,
                void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,