camsys_drv : v0.f.0

diff --git a/drivers/media/video/rk_camsys/camsys_internal.h b/drivers/media/video/rk_camsys/camsys_internal.h
index 0634808f1204ecd8a4bf06999b1d8e5a0968c70a..17ded0c17e02b7cbe11cceb4ed2ffb41e503fd9a 100755 (executable)
--- a/drivers/media/video/rk_camsys/camsys_internal.h
+++ b/drivers/media/video/rk_camsys/camsys_internal.h
@@ -83,6 +83,8 @@
 *        1) add Isp_SoftRst for rk3288;
 *v0.e.0:
 *        1) isp_clk 208.8M for 1lane, isp_clk 416.6M for 2lane;
+*v0.f.0:
+                1) mi_mis register may read erro, this may cause mistaken mi frame_end irqs.  
 */
 #define CAMSYS_DRIVER_VERSION                   KERNEL_VERSION(0,0xe,0)
 

diff --git a/drivers/media/video/rk_camsys/camsys_marvin.c b/drivers/media/video/rk_camsys/camsys_marvin.c
index 07e5f124123afb89993b526890e60a30e9b45296..1a95ec56dc707c8d312115e393379e3d63a19614 100755 (executable)
--- a/drivers/media/video/rk_camsys/camsys_marvin.c
+++ b/drivers/media/video/rk_camsys/camsys_marvin.c
@@ -245,7 +245,6 @@ static int camsys_mrv_clkin_cb(void *ptr, unsigned int on)
     
     return 0;
 }
-
 static int camsys_mrv_clkout_cb(void *ptr, unsigned int on,unsigned int inclk)
 {
     camsys_dev_t *camsys_dev = (camsys_dev_t*)ptr;
@@ -283,14 +282,28 @@ static irqreturn_t camsys_mrv_irq(int irq, void *data)
     camsys_irqstas_t *irqsta;
     camsys_irqpool_t *irqpool;
     unsigned int isp_mis,mipi_mis,mi_mis,*mis;
+       
+       unsigned int mi_ris,mi_imis;
 
     isp_mis = __raw_readl((void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_ISP_MIS));
     mipi_mis = __raw_readl((void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MIPI_MIS));
-    mi_mis = __raw_readl((void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_MIS));    
+
+       mi_mis = __raw_readl((void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_MIS));
+#if 1  
+       mi_ris =  __raw_readl((void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_RIS));
+       mi_imis = __raw_readl((void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_IMIS));
+       while((mi_ris & mi_imis) != mi_mis){
+               camsys_trace(2,"mi_mis status erro,mi_mis 0x%x,mi_ris 0x%x,imis 0x%x\n",mi_mis,mi_ris,mi_imis);
+               mi_mis = __raw_readl((void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_MIS));
+               mi_ris =  __raw_readl((void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_RIS));
+       mi_imis = __raw_readl((void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_IMIS));
+       }
+
+#endif
 
     __raw_writel(isp_mis, (void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_ISP_ICR)); 
     __raw_writel(mipi_mis, (void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MIPI_ICR)); 
-    __raw_writel(mi_mis, (void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_ICR)); 
+       __raw_writel(mi_mis, (void volatile *)(camsys_dev->devmems.registermem->vir_base + MRV_MI_ICR)); 
 
     spin_lock(&camsys_dev->irq.lock);
     if (!list_empty(&camsys_dev->irq.irq_pool)) {

diff --git a/drivers/media/video/rk_camsys/camsys_marvin.h b/drivers/media/video/rk_camsys/camsys_marvin.h
index 000310a090b49930e8c39df9d8df7a8750564ba9..124bc7f2bee6932f57f307eea4aca7c57035e95a 100755 (executable)
--- a/drivers/media/video/rk_camsys/camsys_marvin.h
+++ b/drivers/media/video/rk_camsys/camsys_marvin.h
@@ -17,6 +17,14 @@
 #define MRV_MIPI_ICR                            (MRV_MIPI_BASE+0x14)
 
 #define MRV_MI_BASE                             (0x1400)
+
+#define MRV_MI_MP_Y_OFFS_CNT_START                   (MRV_MI_BASE+0x14)
+#define MRV_MI_INIT                   (MRV_MI_BASE+0x4)
+#define MRV_MI_MP_Y_BASE_AD                   (MRV_MI_BASE+0x8)
+#define MRV_MI_Y_BASE_AD_SHD                   (MRV_MI_BASE+0x78)
+#define MRV_MI_Y_OFFS_CNT_SHD                   (MRV_MI_BASE+0x80)
+#define MRV_MI_IMIS                              (MRV_MI_BASE+0xf8)
+#define MRV_MI_RIS                              (MRV_MI_BASE+0xfc)
 #define MRV_MI_MIS                              (MRV_MI_BASE+0x100)
 #define MRV_MI_ICR                              (MRV_MI_BASE+0x104)