dt-bindings: Add documentation for rockchip lvds

Add binding documentation for Rockchip SoC LVDS driver.

Change-Id: Ie5bbf6715d9dc6b1f5793f78f3eec96783c4725e
Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/video/rockchip-lvds.txt b/Documentation/devicetree/bindings/video/rockchip-lvds.txt
new file mode 100644 (file)
index 0000000..80529f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/rockchip-lvds.txt
@@ -0,0 +1,74 @@
+Rockchip RK3288 LVDS interface
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-lvds";
+
+- reg: physical base address of the controller and length
+       of memory mapped region.
+- clocks: must include clock specifiers corresponding to entries in the
+       clock-names property.
+- clock-names: must contain "pclk_lvds"
+
+- avdd1v0-supply: regulator phandle for 1.0V analog power
+- avdd1v8-supply: regulator phandle for 1.8V analog power
+- avdd3v3-supply: regulator phandle for 3.3V analog power
+
+- rockchip,grf: phandle to the general register files syscon
+
+- rockchip,data-mapping: should be "vesa" or "jeida",
+       This describes how the color bits are laid out in the
+       serialized LVDS signal.
+- rockchip,data-width : should be <18> or <24>;
+- rockchip,output: should be "rgb", "lvds" or "duallvds",
+       This describes the output face.
+
+Required nodes:
+
+The lvds has two video ports as described by
+       Documentation/devicetree/bindings/media/video-interfaces.txt.
+Their connections are modeled using the OF graph bindings specified in
+       Documentation/devicetree/bindings/graph.txt.
+
+- video port 0 for the VOP inputs
+- video port 1 for either a panel or subsequent encoder
+
+Example:
+       lvds: lvds@ff96c000 {
+               compatible = "rockchip,rk3288-lvds";
+               rockchip,grf = <&grf>;
+               reg = <0xff96c000 0x4000>;
+               clocks = <&cru PCLK_LVDS_PHY>;
+               clock-names = "pclk_lvds";
+               avdd1v0-supply = <&vdd10_lcd>;
+               avdd1v8-supply = <&vcc18_lcd>;
+               avdd3v3-supply = <&vcca_33>;
+               rockchip,data-mapping = "jeida";
+               rockchip,data-width = <24>;
+               rockchip,output = "rgb";
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       lvds_in: port@0 {
+                               reg = <0>;
+
+                               lvds_in_vopb: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vopb_out_lvds>;
+                               };
+                               lvds_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_lvds>;
+                               };
+                       };
+
+                       lvds_out: port@1 {
+                               reg = <1>;
+
+                               lvds_out_panel: endpoint {
+                                       remote-endpoint = <&panel_in>;
+                               };
+                       };
+               };
+       };