* Removed unused classes: the rd field is always mentioned as the last reg.

* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6560 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SparcV9/SparcV9_F3.td b/lib/Target/SparcV9/SparcV9_F3.td
index 160f431433ad6306d004e88e3909b1c3547a4b2f..1ba5a6702a3970ca2023e148c121ce3bff92d143 100644 (file)
--- a/lib/Target/SparcV9/SparcV9_F3.td
+++ b/lib/Target/SparcV9/SparcV9_F3.td
@@ -14,45 +14,15 @@ class F3 : InstV9 {
   set Inst{24-19} = op3;
 }
 
-class F3_rd : F3 {
-  bits<5> rd;
-  set Inst{29-25} = rd;
-}
-
-class F3_rdsimm13 : F3_rd {
-  bits<13> simm13;
-  set Inst{12-0} = simm13;
-}
-
-class F3_rdsimm13rs1 : F3_rdsimm13 {
-  bits<5> rs1;
-  set Inst{18-14} = rs1;
-}
-
-// F3_rdrs1 - Common superclass of instructions that use rd & rs1
-class F3_rdrs1 : F3_rd {
-  bits<5> rs1;
-  set Inst{18-14} = rs1;
-}
-
-// F3_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
-class F3_rdrs1rs2 : F3_rdrs1 {
-  bits<5> rs2;
-  set Inst{4-0} = rs2;
-}
-
-// F3_rs1 - Common class of instructions that do not have an rd field,
-// but start at rs1
+// F3_rs1 - Common class of instructions that have an rs1 field
 class F3_rs1 : F3 {
   bits<5> rs1;
-  //set Inst{29-25} = dontcare;
   set Inst{18-14} = rs1;
 }
 
 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
 class F3_rs1rs2 : F3_rs1 {
   bits<5> rs2;
-  //set Inst{12-5} = dontcare;
   set Inst{4-0} = rs2;
 }
 
@@ -74,6 +44,12 @@ class F3_rs1simm13rd : F3_rs1simm13 {
   set Inst{29-25} = rd;
 }
 
+// F3_rs1rd - Common class of instructions that have an rs1 and rd fields
+class F3_rs1rd : F3_rs1 {
+  bits<5> rd;
+  set Inst{29-25} = rd;
+}
+
 // F3_rs2 - Common class of instructions that don't use an rs1
 class F3_rs2 : F3 {
   bits<5> rs2;
@@ -86,6 +62,12 @@ class F3_rs2rd : F3_rs2 {
   set Inst{29-25} = rd;
 }
 
+// F3_rd - Common class of instructions that only have an rd field
+class F3_rd : F3 {
+  bits<5> rd;
+  set Inst{29-25} = rd;
+}
+
 
 // Specific F3 classes...
 //
@@ -105,26 +87,6 @@ class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
   set Inst{13} = 1;   // i field = 1
 }
 
-#if 0
-// The ordering is actually incorrect in these: in the assemble syntax,
-// rd appears last!
-class F3_1a<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
-  set op  = opVal;
-  set op3 = op3val;
-  set Name = name;
-  set Inst{13} = 0;   // i field = 0
-  //set Inst{12-5} = dontcare;
-}
-
-class F3_2a<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
-  set op  = opVal;
-  set op3 = op3val;
-  set Name = name;
-  set Inst{13} = 1;   // i field = 1
-}
-#endif
-
-
 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
   set op   = opVal;
   set op3  = op3val;
@@ -165,7 +127,7 @@ class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
 
 //FIXME: classes 7-10 not defined!!
 
-class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
+class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rs2rd {
   bit x;
   set op = opVal;
   set op3 = op3Val;
@@ -175,14 +137,14 @@ class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
   //set Inst{11-5} = dontcare;
 }
 
-class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
+class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
   bits<5> shcnt;
-  bits<5> rs1;
+  bits<5> rd;
 
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
-  set Inst{18-14} = rs1;
+  set Inst{29-25} = rd;
   set Inst{13} = 1; // i field = 1
   set Inst{12} = 0; // x field = 0
   //set Inst{11-5} = dontcare;
@@ -213,14 +175,14 @@ class F3_14<bits<2> opVal, bits<6> op3Val,
 }
   
 class F3_16<bits<2> opVal,  bits<6> op3Val,
-            bits<9> opfval, string name> : F3_rdrs1rs2 {
+            bits<9> opfval, string name> : F3_rs1rs2rd {
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
   set Inst{13-5} = opfval;
 }
 
-class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 {
+class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rd {
   set op = opVal;
   set op3 = op3Val;
   set Name = name;