#if defined(CONFIG_VCODEC_MMU)
struct list_head mem_region_list;
#endif
- unsigned long *reg;
+ u32 *reg;
} vpu_reg;
typedef struct vpu_device {
};
typedef struct vpu_request {
- unsigned long *req;
+ u64 req;
u32 size;
} vpu_request;
#if VCODEC_CLOCK_ENABLE
switch (pservice->dev_id) {
case VCODEC_DEVICE_ID_HEVC:
- pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
- if (IS_ERR(pservice->clk_cabac)) {
- dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
- return -1;
- }
-
pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
if (IS_ERR(pservice->pd_video)) {
dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
return -1;
}
case VCODEC_DEVICE_ID_COMBO:
+ pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
+ if (IS_ERR(pservice->clk_cabac)) {
+ dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
+ pservice->clk_cabac = NULL;
+ }
pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
if (IS_ERR(pservice->clk_core)) {
dev_err(pservice->dev, "failed on clk_get clk_core\n");
static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
{
- unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
+ u32 type = (reg->reg[3] & 0xF0000000) >> 28;
return ((type == 8) || (type == 4));
}
static inline bool reg_check_interlace(vpu_reg *reg)
{
- unsigned long type = (reg->reg[3] & (1 << 23));
+ u32 type = (reg->reg[3] & (1 << 23));
return (type > 0);
}
reg->type = session->type;
reg->size = size;
reg->freq = VPU_FREQ_DEFAULT;
- reg->reg = (unsigned long *)®[1];
+ reg->reg = (u32 *)®[1];
INIT_LIST_HEAD(®->session_link);
INIT_LIST_HEAD(®->status_link);
VEPU_CLEAN_CACHE(dst);
- dsb();
+ dsb(sy);
dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
HEVC_CLEAN_CACHE(dst);
}
- dsb();
+ dsb(sy);
if (data->hw_info->hw_id != HEVC_ID) {
dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
} else {
dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
}
- dsb();
- dmb();
+ dsb(sy);
+ dmb(sy);
#if VPU_SERVICE_SHOW_TIME
do_gettimeofday(&dec_start);
#endif
for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
dst[i] = src[i];
- dsb();
+ dsb(sy);
dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
#if VPU_SERVICE_SHOW_TIME
dst[i] = src[i];
dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
- dsb();
+ dsb(sy);
dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
};
};
- vpu: vpu_service@ff9a0000 {
- compatible = "vpu_service";
+ vpu: vpu_service {
+ compatible = "rockchip,vpu_sub";
iommu_enabled = <0>;
- reg = <0x0 0xff9a0000 0x0 0x800>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
- /*
- clocks = <&clk_vdpu>, <&hclk_vdpu>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- */
+ dev_mode = <0>;
name = "vpu_service";
- /* status = "disabled"; */
+ };
+
+ hevc: hevc_service {
+ compatible = "rockchip,hevc_sub";
+ iommu_enabled = <0>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irq_dec";
+ dev_mode = <1>;
+ name = "hevc_service";
+ };
+
+ vpu_combo: vpu_combo@ff9a0000 {
+ compatible = "rockchip,vpu_combo";
+ reg = <0x0 0xff9a0000 0x0 0x800>;
+ rockchip,grf = <&grf>;
+ subcnt = <2>;
+ rockchip,sub = <&vpu>, <&hevc>;
+ clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
+ mode_bit = <12>;
+ mode_ctrl = <0x418>;
+ name = "vpu_combo";
+ status = "okay";
};
iep: iep@ff900000 {