Insert missing coherency in comment. Add a quick check for hardware

divide support also.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114813 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 7d56745d1b027c5cdfbe01d2403a11b6020bb9bd..e84989c10bb2286ce3eba8464d488fd90c6a7640 100644 (file)
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -1144,9 +1144,13 @@ bool ARMFastISel::SelectSDiv(const Instruction *I) {
   const Type *Ty = I->getType();
   if (!isTypeLegal(Ty, VT))
     return false;
-    
-  // If we have integer div support we should have gotten already, emit a
-  // libcall.
+
+  // If we have integer div support we should have selected this automagically.
+  // In case we have a real miss go ahead and return false and we'll pick
+  // it up later.
+  if (Subtarget->hasDivide()) return false;  
+  
+  // Otherwise emit a libcall.
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
   if (VT == MVT::i16)
     LC = RTLIB::SDIV_I16;