crc32 with 64-bit output zeros upper 32-bits. rdar://9467055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131664 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 9b985f94ad423e0902697ba26b827e13ea40b684..be8650ec0793dfb39d10f6943833a2ef79eb7dd3 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -10939,6 +10939,19 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
     KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
                                        Mask.getBitWidth() - 1);
     break;
+
+  case ISD::INTRINSIC_WO_CHAIN: {
+    unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+    switch (IntNo) {
+      default: break;
+      case Intrinsic::x86_sse42_crc64_8:
+      case Intrinsic::x86_sse42_crc64_64:
+        // crc32 with 64-bit destination zeros high 32-bit.
+        KnownZero |= APInt::getHighBitsSet(64, 32);
+        break;
+    }
+    break;
+  }
   }
 }
 

diff --git a/test/CodeGen/X86/crc64.ll b/test/CodeGen/X86/crc64.ll
new file mode 100644 (file)
index 0000000..1e0aa0d
--- /dev/null
+++ b/test/CodeGen/X86/crc64.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86-64 -mattr=sse42 | FileCheck %s
+
+; crc32 with 64-bit destination zeros high 32-bit.
+; rdar://9467055
+
+define i64 @t() nounwind {
+entry:
+; CHECK: t:
+; CHECK: crc32q
+; CHECK-NOT: mov
+; CHECK-NEXT: crc32q
+  %0 = tail call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 4) nounwind
+  %1 = and i64 %0, 4294967295
+  %2 = tail call i64 @llvm.x86.sse42.crc64.64(i64 %1, i64 4) nounwind
+  %3 = and i64 %2, 4294967295
+  ret i64 %3
+}
+
+declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone