ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.

commit 43c734be5571a4daad9f0a3e0b3229a1c0049917 upstream.

This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and
PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3
bits.

The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits
[19:17] for Way size, however the existing code only uses 2 bits to
get this value. This results in incorrect cachesize calculations.

It also results in performing operations on the whole cache when we
erroneously decide that the range is big enough (due to l2x0_size being
too small) and also prints incorrect cachesize.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 16bd48031583da44b7c0f25c68027fd787dc3fe1..bfa706ffd9683966dec63406c35e2e71942bd294 100644 (file)
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -64,7 +64,7 @@
 #define L2X0_AUX_CTRL_MASK                     0xc0000fff
 #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT      16
 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT           17
-#define L2X0_AUX_CTRL_WAY_SIZE_MASK            (0x3 << 17)
+#define L2X0_AUX_CTRL_WAY_SIZE_MASK            (0x7 << 17)
 #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT     22
 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT                26
 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT                27