ARM load instruction shifted register index operands.

Parsing and encoding for shifted index operands for load instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 5425c91e9d50c7c2cb7c4ab72ee474eac075fec6..7cfed1de6daf367619ed6820dc60263d51edff93 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -226,7 +226,7 @@ class ARMOperand : public MCParsedAsmOperand {
       const MCConstantExpr *OffsetImm;  // Offset immediate value
       unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
       ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
-      unsigned ShiftValue;      // shift for OffsetReg.
+      unsigned ShiftImm;      // shift for OffsetReg.
       unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
     } Mem;
 
@@ -838,7 +838,7 @@ public:
   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 3 && "Invalid number of operands!");
     unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
-                                     Mem.ShiftValue, Mem.ShiftType);
+                                     Mem.ShiftImm, Mem.ShiftType);
     Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
     Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
     Inst.addOperand(MCOperand::CreateImm(Val));
@@ -1028,7 +1028,7 @@ public:
                                const MCConstantExpr *OffsetImm,
                                unsigned OffsetRegNum,
                                ARM_AM::ShiftOpc ShiftType,
-                               unsigned ShiftValue,
+                               unsigned ShiftImm,
                                bool isNegative,
                                SMLoc S, SMLoc E) {
     ARMOperand *Op = new ARMOperand(Memory);
@@ -1036,7 +1036,7 @@ public:
     Op->Mem.OffsetImm = OffsetImm;
     Op->Mem.OffsetRegNum = OffsetRegNum;
     Op->Mem.ShiftType = ShiftType;
-    Op->Mem.ShiftValue = ShiftValue;
+    Op->Mem.ShiftImm = ShiftImm;
     Op->Mem.isNegative = isNegative;
     Op->StartLoc = S;
     Op->EndLoc = E;
@@ -1916,6 +1916,11 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
 
   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
   unsigned ShiftImm = 0;
+  if (Parser.getTok().is(AsmToken::Comma)) {
+    Parser.Lex(); // Eat the ','.
+    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
+      return MatchOperand_ParseFail;
+  }
 
   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
                                                   ShiftImm, S, E));
@@ -2117,10 +2122,10 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
 
   // If there's a shift operator, handle it.
   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
-  unsigned ShiftValue = 0;
+  unsigned ShiftImm = 0;
   if (Parser.getTok().is(AsmToken::Comma)) {
     Parser.Lex(); // Eat the ','.
-    if (parseMemRegOffsetShift(ShiftType, ShiftValue))
+    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
       return true;
   }
 
@@ -2131,7 +2136,7 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   Parser.Lex(); // Eat right bracket token.
 
   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
-                                           ShiftType, ShiftValue, isNegative,
+                                           ShiftType, ShiftImm, isNegative,
                                            S, E));
 
   // If there's a pre-indexing writeback marker, '!', just add it as a token

diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s
index 765a96e8aa84d303620922786b74d944c23d70e9..64f0ebdd9e8a44430b99ef78cb34d9fa4f0fea49 100644 (file)
--- a/test/MC/ARM/arm-memory-instructions.s
+++ b/test/MC/ARM/arm-memory-instructions.s
@@ -33,6 +33,8 @@ _func:
         ldr r6, [r7, -r8]!
         ldr r5, [r9], r2
         ldr r4, [r3], -r6
+        ldr r3, [r8, -r2, lsl #15]
+        ldr r1, [r5], r3, asr #15
 
 @ CHECK: ldr   r3, [r8, r1]            @ encoding: [0x01,0x30,0x98,0xe7]
 @ CHECK: ldr   r2, [r5, -r3]           @ encoding: [0x03,0x20,0x15,0xe7]
@@ -40,3 +42,5 @@ _func:
 @ CHECK: ldr   r6, [r7, -r8]!          @ encoding: [0x08,0x60,0x37,0xe7]
 @ CHECK: ldr   r5, [r9], r2            @ encoding: [0x02,0x50,0x99,0xe6]
 @ CHECK: ldr   r4, [r3], -r6           @ encoding: [0x06,0x40,0x13,0xe6]
+@ CHECK: ldr   r3, [r8, -r2, lsl #15]  @ encoding: [0x82,0x37,0x18,0xe7]
+@ CHECK: ldr   r1, [r5], r3, asr #15   @ encoding: [0xc3,0x17,0x95,0xe6]