rk3368: clk: add CLKOPS_RATE_RK3368_DCLK_LCDC for dclk_vop0

Signed-off-by: dkl <dkl@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rk3368-clocks.dtsi b/arch/arm64/boot/dts/rk3368-clocks.dtsi
index c9ecfefd275525a4e637d3039f489e8dd17a3569..ced1d1b320fb9dd7c4769c5928713ed24ecb5657 100644 (file)
--- a/arch/arm64/boot/dts/rk3368-clocks.dtsi
+++ b/arch/arm64/boot/dts/rk3368-clocks.dtsi
@@ -946,8 +946,10 @@
                                                clock-output-names = "dclk_vop0";
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
-                                               rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
-                                               rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
+                                               rockchip,clkops-idx =
+                                                       <CLKOPS_RATE_RK3368_DCLK_LCDC>;
+                                               rockchip,flags = <CLK_SET_RATE_PARENT>;
+
                                        };
 
                                        dclk_vop0: dclk_vop0_mux {

diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index fa1bbedb7daee4c2dcbfdb3d43325db11d0911ed..8a13320bc50a4cdf977356117ba7d3fb6c559973 100644 (file)
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -783,6 +783,43 @@ const struct clk_ops clkops_rate_3368_auto_parent = {
        .determine_rate = clk_3368_mux_div_determine_rate,
 };
 
+#define RK3368_LIMIT_NPLL (1250*MHZ)
+
+static long clk_3368_dclk_lcdc_determine_rate(struct clk_hw *hw,
+                                             unsigned long rate,
+                                             unsigned long *best_parent_rate,
+                                             struct clk **best_parent_p)
+{
+       struct clk *npll = clk_get(NULL, "clk_npll");
+       unsigned long div, prate, best;
+
+       *best_parent_p = npll;
+
+       div = RK3368_LIMIT_NPLL/rate;
+       /* div should be even */
+       if (div % 2)
+               div = div - 1;
+
+       prate = div * rate;
+       *best_parent_rate = clk_round_rate(npll, prate);
+       best = (*best_parent_rate)/div;
+
+       return best;
+}
+
+static long clk_3368_dclk_lcdc_round_rate(struct clk_hw *hw, unsigned long rate,
+                                         unsigned long *prate)
+{
+       return clk_3368_dclk_lcdc_determine_rate(hw, rate, prate, NULL);
+}
+
+const struct clk_ops clkops_rate_3368_dclk_lcdc = {
+       .determine_rate = clk_3368_dclk_lcdc_determine_rate,
+       .set_rate       = clk_divider_set_rate,
+       .round_rate     = clk_3368_dclk_lcdc_round_rate,
+       .recalc_rate    = clk_divider_recalc_rate,
+};
+
 struct clk_ops_table rk_clkops_rate_table[] = {
        {.index = CLKOPS_RATE_MUX_DIV,          .clk_ops = &clkops_rate_auto_parent},
        {.index = CLKOPS_RATE_EVENDIV,          .clk_ops = &clkops_rate_evendiv},
@@ -799,6 +836,7 @@ struct clk_ops_table rk_clkops_rate_table[] = {
        {.index = CLKOPS_RATE_DDR_DIV2,         .clk_ops = NULL},
        {.index = CLKOPS_RATE_DDR_DIV4,         .clk_ops = NULL},
        {.index = CLKOPS_RATE_RK3368_MUX_DIV_NPLL,   .clk_ops = &clkops_rate_3368_auto_parent},
+       {.index = CLKOPS_RATE_RK3368_DCLK_LCDC, .clk_ops = &clkops_rate_3368_dclk_lcdc},
        {.index = CLKOPS_RATE_I2S,              .clk_ops = NULL},
        {.index = CLKOPS_RATE_CIFOUT,           .clk_ops = NULL},
        {.index = CLKOPS_RATE_UART,             .clk_ops = NULL},

diff --git a/include/dt-bindings/clock/rockchip.h b/include/dt-bindings/clock/rockchip.h
index 765d3ab15740ea3ebc5610f5f448f44277126b56..82e1f6b4b4b2d48def540f579a357696ebfda77f 100644 (file)
--- a/include/dt-bindings/clock/rockchip.h
+++ b/include/dt-bindings/clock/rockchip.h
@@ -68,6 +68,8 @@
 #define CLKOPS_RATE_DDR_DIV2           18
 #define CLKOPS_RATE_DDR_DIV4           19
 #define CLKOPS_RATE_RK3368_MUX_DIV_NPLL 20
+#define CLKOPS_RATE_RK3368_DCLK_LCDC   21
+
 #define CLKOPS_TABLE_END               (~0)
 
 /* pd id */