Only use clairvoyance when defining a register, and then only if it has one use.

This makes allocation independent on the ordering of use-def chains.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103935 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp
index 9449780d82b60c9c4f941557676585f9b72c222d..04aa47e158de750bdecd4a1f77a13be33f306811 100644 (file)
--- a/lib/CodeGen/RegAllocFast.cpp
+++ b/lib/CodeGen/RegAllocFast.cpp
@@ -399,20 +399,6 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
                !Allocatable.test(Hint)))
     Hint = 0;
 
-  // If there is no hint, peek at the first use of this register.
-  if (!Hint && !MRI->use_nodbg_empty(VirtReg)) {
-    MachineInstr &MI = *MRI->use_nodbg_begin(VirtReg);
-    unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
-    // Copy to physreg -> use physreg as hint.
-    if (TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
-        SrcReg == VirtReg && TargetRegisterInfo::isPhysicalRegister(DstReg) &&
-        RC->contains(DstReg) && !UsedInInstr.test(DstReg) &&
-        Allocatable.test(DstReg)) {
-      Hint = DstReg;
-      DEBUG(dbgs() << "%reg" << VirtReg << " gets hint from " << MI);
-    }
-  }
-
   // Take hint when possible.
   if (Hint) {
     assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
@@ -543,9 +529,18 @@ RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
   bool New;
   tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
   LiveReg &LR = LRI->second;
-  if (New)
+  if (New) {
+    // If there is no hint, peek at the only use of this register.
+    if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
+        MRI->hasOneNonDBGUse(VirtReg)) {
+      unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+      // It's a copy, use the destination register as a hint.
+      if (TII->isMoveInstr(*MRI->use_nodbg_begin(VirtReg),
+                           SrcReg, DstReg, SrcSubReg, DstSubReg))
+        Hint = DstReg;
+    }
     allocVirtReg(MI, *LRI, Hint);
-  else
+  } else
     addKillFlag(LR); // Kill before redefine.
   assert(LR.PhysReg && "Register not assigned");
   LR.LastUse = MI;

diff --git a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
index be7431277723d26fd71b1537565f7df9f89302d0..9c28da8dc4589729dce1ff3d15418a8e2c360237 100644 (file)
--- a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
+++ b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
@@ -1,15 +1,11 @@
 ; RUN: llc < %s | FileCheck %s
-; RUN: llc < %s -regalloc=local | FileCheck -check-prefix=LOCAL %s
-; RUN: llc < %s -regalloc=fast | FileCheck -check-prefix=FAST %s
+; RUN: llc < %s -regalloc=local | FileCheck %s
+; RUN: llc < %s -regalloc=fast | FileCheck %s
 ; The first argument of subfc must not be the same as any other register.
 
-; CHECK: subfc r3,r5,r4
-; CHECK: subfze r4,r6
-; LOCAL: subfc r6,r5,r4
-; LOCAL: subfze r3,r3
-; FAST: subfc r3,r5,r4
-; FAST: subfze r4,r6
-
+; CHECK: subfc [[REG:r.]],
+; CHECK-NOT: [[REG]]
+; CHECK: InlineAsm End
 ; PR1357
 
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"