Merge remote-tracking branch 'origin/develop-3.0-jb' into develop-3.0
author黄涛 <huangtao@rock-chips.com>
Tue, 21 Aug 2012 11:55:23 +0000 (19:55 +0800)
committer黄涛 <huangtao@rock-chips.com>
Tue, 21 Aug 2012 11:55:23 +0000 (19:55 +0800)
arch/arm/plat-rk/Kconfig
drivers/mmc/host/rk29_sdmmc.c
drivers/mmc/host/rk29_sdmmc.h
drivers/usb/dwc_otg/dwc_otg_driver.c
drivers/usb/dwc_otg/dwc_otg_hcd.c
drivers/usb/dwc_otg/dwc_otg_pcd.c

index 4d74efde039705738538c142e1cf59badf62ca87..5aa49d777a934a1c557bb30b483e94f23fd8a915 100755 (executable)
@@ -159,10 +159,15 @@ config RK_EARLY_PRINTK
 config RK_DEBUG_UART
        int "Debug UART"
        default 1 if ARCH_RK29
-       default 2 if ARCH_RK30
+       default 2 if ARCH_RK30 || ARCH_RK2928
        help
          Select a UART for debugging. -1 disable.
 
+config RK_USB_UART
+       bool "Support USB UART Bypass Function"
+       depends on ARCH_RK2928 && (RK_DEBUG_UART = 2)
+       default y
+
 config RK_CONSOLE_THREAD
        bool "Console write by thread"
        depends on FIQ_DEBUGGER_CONSOLE
index 82751006aba569da0dd3f592b448815420bcd579..7e5c999f65ae94af02954b2899fea225a3b3818b 100755 (executable)
@@ -98,7 +98,7 @@ int debug_level = 5;
 #define RK29_SDMMC_WAIT_DTO_INTERNVAL   4500  //The time interval from the CMD_DONE_INT to DTO_INT
 #define RK29_SDMMC_REMOVAL_DELAY        2000  //The time interval from the CD_INT to detect_timer react.
 
-#define RK29_SDMMC_VERSION "Ver.4.02 The last modify date is 2012-08-12"
+#define RK29_SDMMC_VERSION "Ver.4.03 The last modify date is 2012-08-21"
 
 #if !defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD) 
 #define RK29_CTRL_SDMMC_ID   0  //mainly used by SDMMC
@@ -832,8 +832,11 @@ static int rk29_sdmmc_start_command(struct rk29_sdmmc *host, struct mmc_command
     }
                        
        rk29_sdmmc_write(host->regs, SDMMC_CMDARG, cmd->arg); // write to SDMMC_CMDARG register
+#if defined(CONFIG_ARCH_RK29)  
        rk29_sdmmc_write(host->regs, SDMMC_CMD, cmd_flags | SDMMC_CMD_START); // write to SDMMC_CMD register
-
+#else
+    rk29_sdmmc_write(host->regs, SDMMC_CMD, cmd_flags | SDMMC_CMD_USE_HOLD_REG |SDMMC_CMD_START); // write to SDMMC_CMD register
+#endif
 
     xbwprintk(1,"\n%s..%d..************.start cmd=%d, arg=0x%x ********  [%s]\n", \
                        __FUNCTION__, __LINE__, cmd->opcode, cmd->arg, host->dma_name);
@@ -1449,8 +1452,12 @@ static void rk29_sdmmc_submit_data(struct rk29_sdmmc *host, struct mmc_data *dat
 static int sdmmc_send_cmd_start(struct rk29_sdmmc *host, unsigned int cmd)
 {
        int tmo = RK29_SDMMC_SEND_START_TIMEOUT*10;//wait 60ms cycle.
-       
-       rk29_sdmmc_write(host->regs, SDMMC_CMD, SDMMC_CMD_START | cmd);         
+
+#if defined(CONFIG_ARCH_RK29)          
+       rk29_sdmmc_write(host->regs, SDMMC_CMD, SDMMC_CMD_START | cmd); 
+#else  
+    rk29_sdmmc_write(host->regs, SDMMC_CMD, SDMMC_CMD_USE_HOLD_REG |SDMMC_CMD_START | cmd);
+#endif    
        while (--tmo && (rk29_sdmmc_read(host->regs, SDMMC_CMD) & SDMMC_CMD_START))
        {
            udelay(2);
index 17b6d2b209b81c89d2725735c8b8f2be86ebd663..33b5999b72699c9b163514473daf32baf2c7e29a 100755 (executable)
@@ -48,7 +48,7 @@
 
 #if defined(CONFIG_ARCH_RK29)
 #define SDMMC_DATA            (0x100)
-#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) || defined(CONFIG_ARCH_RK2928)
+#else
 #define SDMMC_VERID           (0x06c)   //Version ID register
 #define SDMMC_UHS_REG         (0x074)   //UHS-I register
 #define SDMMC_RST_n           (0x078)   //Hardware reset register
 /* Interrupt status & mask register defines(base+0x24) */
 #if defined(CONFIG_ARCH_RK29)
 #define SDMMC_INT_SDIO          RK2818_BIT(16)      //SDIO interrupt
-#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31)  || defined(CONFIG_ARCH_RK2928)
+#else
 #define SDMMC_INT_SDIO          RK2818_BIT(24)      //SDIO interrupt
 #define SDMMC_INT_UNBUSY        RK2818_BIT(16)      //data no busy interrupt
 #endif
 
 /* Command register defines(base+0x2C) */
 #define SDMMC_CMD_START         RK2818_BIT(31)      //start command
+#if !defined(CONFIG_ARCH_RK29)
+#define SDMMC_CMD_USE_HOLD_REG      RK2818_BIT(29)      //Use hold register.
+#define SDMMC_CMD_VOLT_SWITCH       RK2818_BIT(28)      //Voltage switch bit
+#define SDMMC_CMD_BOOT_MODE         RK2818_BIT(27)      //set boot mode.
+#define SDMMC_CMD_DISABLE_BOOT      RK2818_BIT(26)      //disable boot.
+#define SDMMC_CMD_EXPECT_BOOT_ACK   RK2818_BIT(25)      //Expect Boot Acknowledge.
+#define SDMMC_CMD_ENABLE_BOOT       RK2818_BIT(24)      //be set only for mandatory boot mode.
+#endif
 #define SDMMC_CMD_UPD_CLK       RK2818_BIT(21)      //update clock register only
 #define SDMMC_CMD_INIT          RK2818_BIT(15)      //send initialization sequence
 #define SDMMC_CMD_STOP          RK2818_BIT(14)      //stop abort command
 #define RX_WMARK          (0xF)        //RX watermark level set to 15
 #define TX_WMARK          (0x10)       //TX watermark level set to 16
 
-#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31)  || defined(CONFIG_ARCH_RK2928)
+#else
 #define FIFO_DEPTH        (0x100)       //FIFO depth = 256 word
 #define RX_WMARK_SHIFT    (16)
 #define TX_WMARK_SHIFT    (0)
index bee2c69cc91bb2652743101e07407ec0ffa8631d..e6df8f501132f9b10d4bd3b883825287010ec6c5 100755 (executable)
@@ -1295,7 +1295,6 @@ static __devinit int dwc_otg_driver_probe(struct platform_device *pdev)
     clk_disable(ahbclk);
 #endif
 #endif
-//need to be checked @wlf
 #ifdef CONFIG_ARCH_RK2928                
 #ifndef CONFIG_USB20_HOST
     otg_phy_con = (unsigned int*)(USBGRF_UOC1_CON5);
@@ -1417,8 +1416,7 @@ static __devinit int dwc_otg_driver_probe(struct platform_device *pdev)
        dwc_otg_device->phyclk = phyclk;
        dwc_otg_device->ahbclk = ahbclk;
 #endif
-//need to be checked @wlf
-#if 0//def CONFIG_ARCH_RK2928    
+#ifdef CONFIG_ARCH_RK2928      
     otg_phy_con = (unsigned int*)(USBGRF_UOC0_CON5);
         cru_set_soft_reset(SOFT_RST_USBPHY0, true);
        cru_set_soft_reset(SOFT_RST_OTGC0, true);
@@ -2206,7 +2204,7 @@ static __devinit int host20_driver_probe(struct platform_device *pdev)
     ahbclk = clk_get(NULL, "hclk_otg1");
 #endif    
 #ifdef CONFIG_ARCH_RK2928
-    ahbclk = clk_get(NULL, "hclk_otg1");    //need to be checked @wlf
+    ahbclk = clk_get(NULL, "hclk_otg1");   
 #endif 
     if (IS_ERR(ahbclk)) {
             retval = PTR_ERR(ahbclk);
index b2fb7519f5b67cd512bda9441fac0b3edef666e1..96d7508d9860867b6a78c7137661b48bf65b97a1 100755 (executable)
@@ -624,21 +624,15 @@ static int32_t dwc_otg_phy_suspend_cb( void *_p, int suspend)
         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
     }
 #endif
-#if 0//def CONFIG_ARCH_RK2928                
+#ifdef CONFIG_ARCH_RK2928                
     unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5);
-    if(exitsuspend && (pcd->phy_suspend == 1)) {
-        clk_enable(pcd->otg_dev->ahbclk);
-        clk_enable(pcd->otg_dev->phyclk);
-        pcd->phy_suspend = 0;
+    if(suspend) {
         *otg_phy_con1 = (0x01<<16);    // exit suspend.
         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
     }
-    if( !exitsuspend && (pcd->phy_suspend == 0)) {
-        pcd->phy_suspend = 1;
-        *otg_phy_con1 = 0x55 |(0x7f<<16);   // enter suspend.
+    else{
+        *otg_phy_con1 = 0x1D5 |(0x1ff<<16);   // enter suspend.   enable dm,dp Pull-Down Resistor  wlf @2012.8.10
         udelay(3);
-        clk_disable(pcd->otg_dev->phyclk);
-        clk_disable(pcd->otg_dev->ahbclk);
         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
     }
 #endif
@@ -761,9 +755,9 @@ static void dwc_otg_hcd_connect_detect(unsigned long pdata)
     }
     if(dwc_otg_hcd->host_setenable != dwc_otg_hcd->host_enabled){
 #ifdef CONFIG_ARCH_RK30        
-    DWC_PRINT("%s schedule delaywork 0x%x, 0x%x\n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<22));
+    DWC_PRINT("%s schedule delaywork, hprt 0x%08x, grfstatus 0x%08x\n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<22));
 #else //CONFIG_ARCH_RK2928
-    DWC_PRINT("%s schedule delaywork \n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<12));
+    DWC_PRINT("%s schedule delaywork, hprt 0x%08x, grfstatus 0x%08x\n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<12));
 #endif
     schedule_delayed_work(&dwc_otg_hcd->host_enable_work, 8);
     }
@@ -1149,21 +1143,15 @@ static int32_t host20_phy_suspend_cb( void *_p, int suspend)
         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
     }
 #endif
-#if 0//def CONFIG_ARCH_RK2928                
-    unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5);
-    if(exitsuspend && (pcd->phy_suspend == 1)) {
-        clk_enable(pcd->otg_dev->ahbclk);
-        clk_enable(pcd->otg_dev->phyclk);
-        pcd->phy_suspend = 0;
+#ifdef CONFIG_ARCH_RK2928                
+    unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON5);
+     if(suspend) {
         *otg_phy_con1 = (0x01<<16);    // exit suspend.
         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
     }
-    if( !exitsuspend && (pcd->phy_suspend == 0)) {
-        pcd->phy_suspend = 1;
-        *otg_phy_con1 = 0x55 |(0x7f<<16);   // enter suspend.
+    else{
+        *otg_phy_con1 = 0x1D5 |(0x1ff<<16);   // enter suspend.  enable dm,dp Pull-Down Resistor  wlf @2012.8.10
         udelay(3);
-        clk_disable(pcd->otg_dev->phyclk);
-        clk_disable(pcd->otg_dev->ahbclk);
         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
     }
 #endif
index f2f62ef70cc8b69681c39df0886b7bf8b25f34e5..9faaad28acd2020711098ef9b490ef15614d9edc 100755 (executable)
@@ -87,6 +87,7 @@
 #ifdef CONFIG_ARCH_RK29
 #include <mach/cru.h>
 #endif
+#include <mach/board.h>
 /**
  * Static PCD pointer for use in usb_gadget_register_driver and
  * usb_gadget_unregister_driver.  Initialized in dwc_otg_pcd_init.
@@ -1682,10 +1683,10 @@ int dwc_otg20phy_suspend( int exitsuspend )
     }
     if( !exitsuspend && (pcd->phy_suspend == 0)) {
         pcd->phy_suspend = 1;
-        *otg_phy_con1 = 0x55 |(0x7f<<16);   // enter suspend.
-      //  *otg_phy_con1 = 0x1D5 |(0x1ff<<16);   // enter suspend.   enable dm,dp  debug_wlf @2012.8.10
+        *otg_phy_con1 = 0x1D5 |(0x1ff<<16);   // enter suspend.   enable dm,dp Pull-Down Resistor  wlf @2012.8.10
         udelay(3);
-        clk_disable(pcd->otg_dev->phyclk);
+//  otg/host20 use the same phyclk, so can't disable phyclk in case host20 is used.    wlf @2012.8.16     
+//      clk_disable(pcd->otg_dev->phyclk); 
         clk_disable(pcd->otg_dev->ahbclk);
         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
     }
@@ -1918,7 +1919,6 @@ static void dwc_otg_pcd_check_vbus_timer( unsigned long pdata )
         /* if usb not connect before ,then start connect */
          if( _pcd->vbus_status == 0 ) {
             DWC_PRINT("********vbus detect*********************************************\n");
-            dwc_otg_msc_lock(_pcd);
            _pcd->vbus_status = 1;
             if(_pcd->conn_en)
                 goto connect;
@@ -1935,16 +1935,17 @@ static void dwc_otg_pcd_check_vbus_timer( unsigned long pdata )
             _pcd->conn_status++;
             if((dwc_read_reg32((uint32_t*)((uint8_t *)_pcd->otg_dev->base + DWC_OTG_HOST_PORT_REGS_OFFSET))&0xc00) == 0xc00)
                 _pcd->vbus_status = 2;
+            dwc_otg20phy_suspend(0);
         }
        }else {
         _pcd->vbus_status = 0;
-        if(_pcd->conn_status)
-        {
+        if(_pcd->conn_status){
              _pcd->conn_status = 0;
              dwc_otg_msc_unlock(_pcd);
+           rk28_send_wakeup_key();
         }
         /* every 500 ms open usb phy power and start 1 jiffies timer to get vbus */
-        if( _pcd->phy_suspend == 0 ) 
+        else if( _pcd->phy_suspend == 0 ) 
                 /* no vbus detect here , close usb phy  */
              dwc_otg20phy_suspend( 0 );
     }
@@ -1953,6 +1954,8 @@ static void dwc_otg_pcd_check_vbus_timer( unsigned long pdata )
     return;
 
 connect:
+    if(_pcd->conn_status==0)
+        dwc_otg_msc_lock(_pcd);
     if( _pcd->phy_suspend  == 1 )
          dwc_otg20phy_suspend( 1 );
     schedule_delayed_work( &_pcd->reconnect , 8 ); /* delay 1 jiffies */