implement shl and sra

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30191 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 892c297d8c63ca25aed6dad187e52c63d666437a..c40521bed4d039f17062703e08f8b1417d33abb9 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -113,6 +113,18 @@ def andrr     : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
                       "and $dst, $a, $b",
                       [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
 
+
+// All arm data processing instructions have a shift. Maybe we don't have
+// to implement this
+def SHL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+                      "mov $dst, $a, lsl $b",
+                      [(set IntRegs:$dst, (shl IntRegs:$a, IntRegs:$b))]>;
+
+def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+                      "mov $dst, $a, asr $b",
+                      [(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
+
+
 def eor_rr     : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
                       "eor $dst, $a, $b",
                       [(set IntRegs:$dst, (xor IntRegs:$a, IntRegs:$b))]>;

diff --git a/test/CodeGen/ARM/bits.ll b/test/CodeGen/ARM/bits.ll
new file mode 100644 (file)
index 0000000..ca79e49
--- /dev/null
+++ b/test/CodeGen/ARM/bits.ll
@@ -0,0 +1,36 @@
+; RUN: llvm-as < %s | llc -march=arm &&
+; RUN: llvm-as < %s | llc -march=arm | grep and      | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep orr      | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep eor      | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep mov.*lsl | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep mov.*asr | wc -l | grep 1
+
+int %f1(int %a, int %b) {
+entry:
+       %tmp2 = and int %b, %a          ; <int> [#uses=1]
+       ret int %tmp2
+}
+
+int %f2(int %a, int %b) {
+entry:
+       %tmp2 = or int %b, %a           ; <int> [#uses=1]
+       ret int %tmp2
+}
+
+int %f3(int %a, int %b) {
+entry:
+       %tmp2 = xor int %b, %a          ; <int> [#uses=1]
+       ret int %tmp2
+}
+
+int %f4(int %a, ubyte %b) {
+entry:
+       %tmp3 = shl int %a, ubyte %b            ; <int> [#uses=1]
+       ret int %tmp3
+}
+
+int %f5(int %a, ubyte %b) {
+entry:
+       %tmp3 = shr int %a, ubyte %b            ; <int> [#uses=1]
+       ret int %tmp3
+}