rk312x:clk:fixed frequency div for aclk_core and pclk_dbg

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index c092f831bfcfdd307cd16149621026ebac872428..014f012c1a98485387871b8bc9f89eada79749e5 100755 (executable)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -202,23 +202,23 @@ static const struct apll_clk_set rk3036_apll_table[] = {
        _RK3036_APLL_SET_CLKS(984, 1, 82, 2, 1, 1, 0, 81, 41, 41, 21, 21),
        _RK3036_APLL_SET_CLKS(960, 1, 80, 2, 1, 1, 0, 81, 41, 41, 21, 21),
        _RK3036_APLL_SET_CLKS(936, 1, 78, 2, 1, 1, 0, 81, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(912, 1, 76, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(900, 4, 300, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(888, 1, 74, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(864, 1, 72, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(840, 1, 70, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(816, 1, 68, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(800, 6, 400, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(700, 6, 350, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(696, 1, 58, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(600, 1, 75, 3, 1, 1, 0, 41, 21, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(504, 1, 63, 3, 1, 1, 0, 41, 21, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(500, 6, 250, 2, 1, 1, 0, 41, 21, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(408, 1, 68, 2, 2, 1, 0, 41, 21, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(312, 1, 52, 2, 2, 1, 0, 41, 21, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(216, 1, 72, 4, 2, 1, 0, 41, 21, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(96, 1, 64, 4, 4, 1, 0, 21, 21, 41, 21, 21),
-       _RK3036_APLL_SET_CLKS(0, 1, 0, 1, 1, 1, 0, 21, 21, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(912, 1, 76, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(900, 4, 300, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(888, 1, 74, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(864, 1, 72, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(840, 1, 70, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(816, 1, 68, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(800, 6, 400, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(700, 6, 350, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(696, 1, 58, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(600, 1, 75, 3, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(504, 1, 63, 3, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(500, 6, 250, 2, 1, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(408, 1, 68, 2, 2, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(312, 1, 52, 2, 2, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(216, 1, 72, 4, 2, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(96, 1, 64, 4, 4, 1, 0, 81, 41, 41, 21, 21),
+       _RK3036_APLL_SET_CLKS(0, 1, 0, 1, 1, 1, 0, 81, 41, 41, 21, 21),
 };
 
 static const struct pll_clk_set rk3036plus_pll_com_table[] = {