clk: imx: clk-imx6q: Provide initial IPU clock settings for mx6dl
authorFabio Estevam <fabio.estevam@freescale.com>
Fri, 26 Jun 2015 17:10:54 +0000 (14:10 -0300)
committerShawn Guo <shawnguo@kernel.org>
Mon, 13 Jul 2015 08:35:30 +0000 (16:35 +0800)
Currently it is not possible to use HDMI and LVDS at the same time on a
imx6dl-sabresd board.

Fix this usecase by setting IMX6QDL_CLK_PLL3_PFD1_540M to 540MHz and
also by setting it as the parent of IMX6QDL_CLK_IPU1_SEL.

Based on the configuration done in the FSL kernel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx6q.c

index d046f8e43de8d056d1af2cb1ae4bd790019d2d9a..c507bcad2c37ee4d1af6e9214f0c36769defd1a5 100644 (file)
@@ -494,6 +494,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
        }
 
+       clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
+       if (clk_on_imx6dl())
+               clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
+
        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);