comment
authorAndrew Trick <atrick@apple.com>
Thu, 17 May 2012 18:35:07 +0000 (18:35 +0000)
committerAndrew Trick <atrick@apple.com>
Thu, 17 May 2012 18:35:07 +0000 (18:35 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157005 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineScheduler.cpp
lib/CodeGen/RegisterPressure.cpp

index 41b4b719f27674ed4e356784f72e5d4b20f22400..1d810fdf16d220caa3bc839c188ebf183481d753 100644 (file)
@@ -819,8 +819,6 @@ SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
     assert(TopQueue.empty() && BotQueue.empty() && "ReadyQ garbage");
     return NULL;
   }
-  // As an initial placeholder heuristic, schedule in the direction that has
-  // the fewest choices.
   SUnit *SU;
   if (ForceTopDown) {
     SU = DAG->getSUnit(DAG->top());
index fbd08cb575aa29638d2bd01fb0883b22a1e66ec9..912ed0dd7b149a5bb42c6366d24e674cafef49bb 100644 (file)
@@ -698,7 +698,7 @@ getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta) {
       unsigned Reg = VirtRegOpers.Uses[i];
       const LiveInterval *LI = &LIS->getInterval(Reg);
       // FIXME: allow the caller to pass in the list of vreg uses that remain to
-      // be top-scheduled to avoid searching uses at each query.
+      // be bottom-scheduled to avoid searching uses at each query.
       SlotIndex CurrIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
       if (LI->killedAt(SlotIdx)
           && !findUseBetween(Reg, CurrIdx, SlotIdx, MRI, LIS)) {