Force fragile test to the atom scheduler model.

The pattern the test originally checked for doesn't occur on other -mcpu
settings. On atom it's still there though slightly differently scheduled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182933 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/zext-sext.ll b/test/CodeGen/X86/zext-sext.ll
index 2459f1fa254a405ed791cd725fb410c34361613f..87a6099c0ca6907f50573d907ea2b96c1b56d4a9 100644 (file)
--- a/test/CodeGen/X86/zext-sext.ll
+++ b/test/CodeGen/X86/zext-sext.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mcpu=atom | FileCheck %s
 ; <rdar://problem/8006248>
 
 ; This randomly started passing after an unrelated change, if it fails again it
@@ -34,9 +34,11 @@ entry:
   %tmp12 = add i64 %tmp11, 5089792279245435153
 
 ; CHECK:      addl     $2138875574, %e[[REGISTER_zext:[a-z0-9]+]]
+; CHECK-NEXT: cmpl     $-8608074, %e[[REGISTER_zext]]
 ; CHECK-NEXT: movslq   %e[[REGISTER_zext]], [[REGISTER_tmp:%r[a-z0-9]+]]
 ; CHECK:      movq     [[REGISTER_tmp]], [[REGISTER_sext:%r[a-z0-9]+]]
-; CHECK-NEXT: subq     %r[[REGISTER_zext]], [[REGISTER_sext]]
+; CHECK-NOT:  [[REGISTER_zext]]
+; CHECK:      subq     %r[[REGISTER_zext]], [[REGISTER_sext]]
 
   %tmp13 = sub i64 %tmp12, 2138875574
   %tmp14 = zext i32 %tmp4 to i64