Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if

the instruction is predicated, reg0 otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index c0d282086f3924a0d48fe8feb6f4d27431d2a8c1..005bfc93bef722d18c03063278fa226a36f4afd6 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -263,8 +263,8 @@ public:
   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
-    // FIXME: What belongs here?
-    Inst.addOperand(MCOperand::CreateReg(0));
+    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
+    Inst.addOperand(MCOperand::CreateReg(RegNum));
   }
 
   void addCCOutOperands(MCInst &Inst, unsigned N) const {