Emit correct DWARF reg # for RA (return address) register

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36646 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index e5f57ca24e02e0666de7219340d1707776e432df..4795319a28153681eac7b9b77215418fc1b8bbeb 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -1235,7 +1235,10 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
 }
 
 unsigned X86RegisterInfo::getRARegister() const {
-  return X86::ST0;  // use a non-register register
+  if (Is64Bit)
+    return X86::RIP;  // Should have dwarf #16
+  else
+    return X86::EIP;  // Should have dwarf #8
 }
 
 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 7727a674161135196e46ddb581b30cef9e33174a..089078a3ae8af2771a94e5ed8e4f259985a0d597 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -60,6 +60,7 @@ let Namespace = "X86" in {
   def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<5>;
   def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<6>;
   def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<7>;
+  def IP : Register<"IP">, DwarfRegNum<8>;  
   
   // X86-64 only
   def R8W  : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>;
@@ -80,6 +81,7 @@ let Namespace = "X86" in {
   def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<5>;
   def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<6>;
   def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<7>;
+  def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<8>;  
   
   // X86-64 only
   def R8D  : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>;
@@ -109,6 +111,7 @@ let Namespace = "X86" in {
   def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>;
   def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>;
   def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>;
+  def RIP : RegisterWithSubRegs<"RIP", [EIP]>,  DwarfRegNum<16>;
 
   // MMX Registers. These are actually aliased to ST0 .. ST7
   def MM0 : Register<"MM0">, DwarfRegNum<29>;