Cosmetic changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122259 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c54da0dd398c65abb7ccb7d7ad1430c94ff54c2f..c1288d5d7bed08b6cc27832b23feed1c9162b08d 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3172,15 +3172,15 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
   }
 
   // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
-  // This is only valid if the OpSizeInBits + c1 = size of inner shift
   if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
       N0.getOperand(0).getOpcode() == ISD::SRL &&
-      N0.getOperand(0)->getOperand(1).getOpcode() == ISD::Constant) {
+      isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
     uint64_t c1 = 
       cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
     uint64_t c2 = N1C->getZExtValue();
     EVT InnerShiftVT = N0.getOperand(0)->getOperand(1).getValueType();
     uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
+    // This is only valid if the OpSizeInBits + c1 = size of inner shift.
     if (c1 + OpSizeInBits == InnerShiftSize) {
       if (c1 + c2 >= InnerShiftSize)
         return DAG.getConstant(0, VT);

diff --git a/test/CodeGen/X86/x86_64-mul-by-const.ll b/test/CodeGen/X86/x86_64-mul-by-const.ll
index 9cda9ab192aace1dc8d9bce880b5975c7abea88d..df48a29156caa5bc6b66e2c8408c78b2521ba66a 100644 (file)
--- a/test/CodeGen/X86/x86_64-mul-by-const.ll
+++ b/test/CodeGen/X86/x86_64-mul-by-const.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
-; Formerly there were two shifts.  8771012.
+; Formerly there were two shifts.  rdar://8771012.
 
 define i32 @f9188_mul365384439_shift27(i32 %A) nounwind {
 ; CHECK:  imulq $365384439,