Legalizer: Add an assert and tweak a comment to clarify the assumptions this code...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173620 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index e08dd6dcb6d1176ec4b7d41bbdf2de58c3586b1d..88e72ecd92979fadf31af58562e415cedef81371 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2098,9 +2098,13 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
     EVT VT = LHSL.getValueType();
 
     // If the shift amount operand is coming from a vector legalization it may
-    // not have the right return type.  Fix that first by casting the operand.
+    // have an illegal type.  Fix that first by casting the operand.  Otherwise
+    // the new SHL_PARTS operation would need further legalization, and the
+    // legalizer assumes that illegal SHL_PARTS never occur.
     SDValue ShiftOp = N->getOperand(1);
     MVT ShiftTy = TLI.getShiftAmountTy(VT);
+    assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(VT.getSizeInBits()) &&
+           "ShiftAmountTy is too small to cover the range of this type!");
     if (ShiftOp.getValueType() != ShiftTy)
       ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);