The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter
slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and
add a special operand class for the parameter slots for type checking and
pretty printing.
NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175193
91177308-0d34-0410-b5e6-
96231b3b80d8
}
}
+void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O) {
+ unsigned Imm = MI->getOperand(OpNum).getImm();
+
+ if (Imm == 2) {
+ O << "P0";
+ } else if (Imm == 1) {
+ O << "P20";
+ } else if (Imm == 0) {
+ O << "P10";
+ } else {
+ assert(!"Invalid interpolation parameter slot");
+ }
+}
+
void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
printOperand(MI, OpNo, O);
private:
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+ void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm);
void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
case AMDGPU::SI_INTERP:
LowerSI_INTERP(MI, *BB, I, MRI);
break;
- case AMDGPU::SI_INTERP_CONST:
- LowerSI_INTERP_CONST(MI, *BB, I, MRI);
- break;
case AMDGPU::SI_WQM:
LowerSI_WQM(MI, *BB, I, MRI);
break;
MI->eraseFromParent();
}
-void SITargetLowering::LowerSI_INTERP_CONST(MachineInstr *MI,
- MachineBasicBlock &BB, MachineBasicBlock::iterator I,
- MachineRegisterInfo &MRI) const {
- MachineOperand dst = MI->getOperand(0);
- MachineOperand attr_chan = MI->getOperand(1);
- MachineOperand attr = MI->getOperand(2);
- MachineOperand params = MI->getOperand(3);
- unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
-
- BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
- .addOperand(params);
-
- BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_MOV_F32))
- .addOperand(dst)
- .addOperand(attr_chan)
- .addOperand(attr)
- .addReg(M0);
-
- MI->eraseFromParent();
-}
-
void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
unsigned VCC = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
MachineBasicBlock::iterator I, unsigned Opocde) const;
void LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
- void LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB,
- MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
void LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
// that are not yet supported remain commented out.
//===----------------------------------------------------------------------===//
+class InterpSlots {
+int P0 = 2;
+int P10 = 0;
+int P20 = 1;
+}
+def INTERP : InterpSlots;
+
+def InterpSlot : Operand<i32> {
+ let PrintMethod = "printInterpSlot";
+}
+
def isSI : Predicate<"Subtarget.device()"
"->getGeneration() == AMDGPUDeviceInfo::HD7XXX">;
def V_INTERP_MOV_F32 : VINTRP <
0x00000002,
(outs VReg_32:$dst),
- (ins i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
- "V_INTERP_MOV_F32",
+ (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
+ "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr",
[]> {
- let VSRC = 0;
let DisableEncoding = "$m0";
}
[]
>;
-def SI_INTERP_CONST : InstSI <
- (outs VReg_32:$dst),
- (ins i32imm:$attr_chan, i32imm:$attr, SReg_32:$params),
- "SI_INTERP_CONST $dst, $attr_chan, $attr, $params",
- [(set VReg_32:$dst, (int_SI_fs_interp_constant imm:$attr_chan,
- imm:$attr, SReg_32:$params))]
->;
-
def SI_WQM : InstSI <
(outs),
(ins),
/********** Interpolation Paterns **********/
/********** ===================== **********/
+def : Pat <
+ (int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, SReg_32:$params),
+ (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, SReg_32:$params)
+>;
+
def : Pat <
(int_SI_fs_interp_linear_center imm:$attr_chan, imm:$attr, SReg_32:$params),
(SI_INTERP (f32 LINEAR_CENTER_I), (f32 LINEAR_CENTER_J), imm:$attr_chan,