clk: rockchip: rk3399: Add more pll rates for HDMI

Modify the 594MHz parameter for higher VCO freq to reduce the jitter.

Change-Id: I78784210b69d6895758192c84724b982fcc9e72d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 356e132562421f3a002b52c9e68e8be168e3d1c3..c8f80400e58c5881a2ca6435a92c400eec9bb222 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -92,13 +92,18 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
        RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
        RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
        RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
-       RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
+       RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
        RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
        RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
        RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
        RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
+       RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
        RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
+       RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
        RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
+       RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),
+       RK3036_PLL_RATE(  54000000, 1, 54, 6, 4, 1, 0),
+       RK3036_PLL_RATE(  27000000, 1, 27, 6, 4, 1, 0),
        { /* sentinel */ },
 };