we no longer need to find the live-before set of the delayed
branch since that set is now included the live-before/after
set of the instructions in each delay slot. Just assert that instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7796
91177308-0d34-0410-b5e6-
96231b3b80d8
#include "llvm/Type.h"
#include "llvm/iOther.h"
#include "Support/STLExtras.h"
#include "llvm/Type.h"
#include "llvm/iOther.h"
#include "Support/STLExtras.h"
+#include "Support/SetOperations.h"
#include "Support/CommandLine.h"
#include <math.h>
using std::cerr;
#include "Support/CommandLine.h"
#include <math.h>
using std::cerr;
RegClass *RC = LR->getRegClass();
// Get the live-variable set to find registers free before this instr.
RegClass *RC = LR->getRegClass();
// Get the live-variable set to find registers free before this instr.
- // If this instr. is in the delay slot of a branch or return, use the live
- // var set before that branch or return -- we don't want to trample those!
+ const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
+
+#ifndef NDEBUG
+ // If this instr. is in the delay slot of a branch or return, we need to
+ // include all live variables before that branch or return -- we don't want to
+ // trample those! Verify that the set is included in the LV set before MInst.
- MachineInstr *LiveBeforeThisMI = MInst;
if (MII != MBB.begin()) {
MachineInstr *PredMI = *(MII-1);
if (MII != MBB.begin()) {
MachineInstr *PredMI = *(MII-1);
- if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode())) {
- assert(DS == 1 && "Only checking immediate pred. for delay slots!");
- LiveBeforeThisMI = PredMI;
- }
+ if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
+ assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
+ .empty() && "Live-var set before branch should be included in "
+ "live-var set of each delay slot instruction!");
- const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(LiveBeforeThisMI,BB);
MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
const MachineInstr *DelayedMI)
{
void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
const MachineInstr *DelayedMI)
{
+ // "added after" instructions of the original instr
+ std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
+
+ if (DEBUG_RA && OrigAft.size() > 0) {
cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
cerr << " to last delay slot instrn: " << *DelayedMI;
}
cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
cerr << " to last delay slot instrn: " << *DelayedMI;
}
- // "added after" instructions of the original instr
- std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
-
// "added after" instructions of the delayed instr
std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;
// "added after" instructions of the delayed instr
std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;
#include "llvm/Type.h"
#include "llvm/iOther.h"
#include "Support/STLExtras.h"
#include "llvm/Type.h"
#include "llvm/iOther.h"
#include "Support/STLExtras.h"
+#include "Support/SetOperations.h"
#include "Support/CommandLine.h"
#include <math.h>
using std::cerr;
#include "Support/CommandLine.h"
#include <math.h>
using std::cerr;
RegClass *RC = LR->getRegClass();
// Get the live-variable set to find registers free before this instr.
RegClass *RC = LR->getRegClass();
// Get the live-variable set to find registers free before this instr.
- // If this instr. is in the delay slot of a branch or return, use the live
- // var set before that branch or return -- we don't want to trample those!
+ const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
+
+#ifndef NDEBUG
+ // If this instr. is in the delay slot of a branch or return, we need to
+ // include all live variables before that branch or return -- we don't want to
+ // trample those! Verify that the set is included in the LV set before MInst.
- MachineInstr *LiveBeforeThisMI = MInst;
if (MII != MBB.begin()) {
MachineInstr *PredMI = *(MII-1);
if (MII != MBB.begin()) {
MachineInstr *PredMI = *(MII-1);
- if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode())) {
- assert(DS == 1 && "Only checking immediate pred. for delay slots!");
- LiveBeforeThisMI = PredMI;
- }
+ if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
+ assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
+ .empty() && "Live-var set before branch should be included in "
+ "live-var set of each delay slot instruction!");
- const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(LiveBeforeThisMI,BB);
MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
const MachineInstr *DelayedMI)
{
void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
const MachineInstr *DelayedMI)
{
+ // "added after" instructions of the original instr
+ std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
+
+ if (DEBUG_RA && OrigAft.size() > 0) {
cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
cerr << " to last delay slot instrn: " << *DelayedMI;
}
cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
cerr << " to last delay slot instrn: " << *DelayedMI;
}
- // "added after" instructions of the original instr
- std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
-
// "added after" instructions of the delayed instr
std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;
// "added after" instructions of the delayed instr
std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;