+// These (dreg triple/quadruple) are for disassembly only.
+class VST1D3<bits<4> op7_4, string OpcodeStr, string Dt>
+ : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
+ (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
+ OpcodeStr, Dt,
+ "\\{$src1, $src2, $src3\\}, $addr", "",
+ [/* For disassembly only; pattern left blank */]>;
+class VST1D4<bits<4> op7_4, string OpcodeStr, string Dt>
+ : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
+ (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
+ IIC_VST, OpcodeStr, Dt,
+ "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
+ [/* For disassembly only; pattern left blank */]>;
+
+def VST1d8T : VST1D3<0b0000, "vld1", "8">;
+def VST1d16T : VST1D3<0b0100, "vld1", "16">;
+def VST1d32T : VST1D3<0b1000, "vld1", "32">;
+//def VST1d64T : VST1D3<0b1100, "vld1", "64">;
+
+def VST1d8Q : VST1D4<0b0000, "vld1", "8">;
+def VST1d16Q : VST1D4<0b0100, "vld1", "16">;
+def VST1d32Q : VST1D4<0b1000, "vld1", "32">;
+//def VST1d64Q : VST1D4<0b1100, "vld1", "64">;
+
+