git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139820
91177308-0d34-0410-b5e6-
96231b3b80d8
class MCInst {
unsigned Opcode;
SmallVector<MCOperand, 8> Operands;
class MCInst {
unsigned Opcode;
SmallVector<MCOperand, 8> Operands;
+ SmallVector<std::string, 1> Annotations;
public:
MCInst() : Opcode(0) {}
public:
MCInst() : Opcode(0) {}
Operands.push_back(Op);
}
Operands.push_back(Op);
}
- void clear() { Operands.clear(); }
+ void addAnnotation(const std::string &Annot) {
+ Annotations.push_back(Annot);
+ }
+
+ void clear() {
+ Operands.clear();
+ Annotations.clear();
+ }
+
size_t size() { return Operands.size(); }
typedef SmallVector<MCOperand, 8>::iterator iterator;
size_t size() { return Operands.size(); }
typedef SmallVector<MCOperand, 8>::iterator iterator;
return Operands.insert(I, Op);
}
return Operands.insert(I, Op);
}
+ size_t getNumAnnotations() const { return Annotations.size(); }
+ std::string getAnnotation(size_t i) const { return Annotations[i]; }
+
void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
void dump() const;
void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
void dump() const;
///
virtual void printInst(const MCInst *MI, raw_ostream &OS) = 0;
///
virtual void printInst(const MCInst *MI, raw_ostream &OS) = 0;
+ /// printAnnotations - Print the annotation comments attached to specified
+ /// MCInst to the specified raw_ostream.
+ void printAnnotations(const MCInst *MI, raw_ostream &OS);
+
/// getOpcodeName - Return the name of the specified opcode enum (e.g.
/// "MOV32ri") or empty if we can't resolve it.
virtual StringRef getOpcodeName(unsigned Opcode) const;
/// getOpcodeName - Return the name of the specified opcode enum (e.g.
/// "MOV32ri") or empty if we can't resolve it.
virtual StringRef getOpcodeName(unsigned Opcode) const;
OS << " ";
getOperand(i).print(OS, MAI);
}
OS << " ";
getOperand(i).print(OS, MAI);
}
+
+ if (getNumAnnotations()) {
+ OS << " # Annots: ";
+ for (unsigned i = 0, e = getNumAnnotations(); i != e; ++i) {
+ OS << " \"";
+ OS << getAnnotation(i);
+ OS << '"';
+ }
+ }
+
OS << Separator;
getOperand(i).print(OS, MAI);
}
OS << Separator;
getOperand(i).print(OS, MAI);
}
+
+ if (getNumAnnotations()) {
+ OS << " # Annots: ";
+ for (unsigned i = 0, e = getNumAnnotations(); i != e; ++i) {
+ OS << Separator;
+ OS << '"';
+ OS << getAnnotation(i);
+ OS << '"';
+ }
+ }
+
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCInstPrinter.h"
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCInst.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
MCInstPrinter::~MCInstPrinter() {
using namespace llvm;
MCInstPrinter::~MCInstPrinter() {
void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
assert(0 && "Target should implement this");
}
void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
assert(0 && "Target should implement this");
}
+
+void MCInstPrinter::printAnnotations(const MCInst *MI, raw_ostream &OS) {
+ for (unsigned i = 0, e = MI->getNumAnnotations(); i != e; ++i) {
+ OS << MI->getAnnotation(i) << "\n";
+ }
+}
O << ", " << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
O << ", " << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
+
+ if (CommentStream) printAnnotations(MI, *CommentStream);
+
O << '\t' << getRegisterName(Dst.getReg())
<< ", " << getRegisterName(MO1.getReg());
O << '\t' << getRegisterName(Dst.getReg())
<< ", " << getRegisterName(MO1.getReg());
- if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx)
+ if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
+ if (CommentStream) printAnnotations(MI, *CommentStream);
O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
+
+ if (CommentStream) printAnnotations(MI, *CommentStream);
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
+ if (CommentStream) printAnnotations(MI, *CommentStream);
return;
}
if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
return;
}
if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
O << '\t' << "push";
printPredicateOperand(MI, 4, O);
O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
O << '\t' << "push";
printPredicateOperand(MI, 4, O);
O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
+ if (CommentStream) printAnnotations(MI, *CommentStream);
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
+ if (CommentStream) printAnnotations(MI, *CommentStream);
return;
}
if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
return;
}
if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
O << '\t' << "pop";
printPredicateOperand(MI, 5, O);
O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
O << '\t' << "pop";
printPredicateOperand(MI, 5, O);
O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
+ if (CommentStream) printAnnotations(MI, *CommentStream);
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
+ if (CommentStream) printAnnotations(MI, *CommentStream);
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
+ if (CommentStream) printAnnotations(MI, *CommentStream);
if (Writeback) O << "!";
O << ", ";
printRegisterList(MI, 3, O);
if (Writeback) O << "!";
O << ", ";
printRegisterList(MI, 3, O);
+ if (CommentStream) printAnnotations(MI, *CommentStream);
MI->getOperand(1).getReg() == ARM::R8) {
O << "\tnop";
printPredicateOperand(MI, 2, O);
MI->getOperand(1).getReg() == ARM::R8) {
O << "\tnop";
printPredicateOperand(MI, 2, O);
+ if (CommentStream) printAnnotations(MI, *CommentStream);
return;
}
printInstruction(MI, O);
return;
}
printInstruction(MI, O);
+ if (CommentStream) printAnnotations(MI, *CommentStream);
}
void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
printInstruction(MI, OS);
// If verbose assembly is enabled, we can print some informative comments.
printInstruction(MI, OS);
// If verbose assembly is enabled, we can print some informative comments.
+ if (CommentStream) {
+ printAnnotations(MI, *CommentStream);
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
}
StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
}
StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
printInstruction(MI, OS);
// If verbose assembly is enabled, we can print some informative comments.
printInstruction(MI, OS);
// If verbose assembly is enabled, we can print some informative comments.
+ if (CommentStream) {
+ printAnnotations(MI, *CommentStream);
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
}
StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
return getInstructionName(Opcode);
}
StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
return getInstructionName(Opcode);