+static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
+{
+ u32 vsctrl, vbbase, vscadr, vsadr;
+ u32 sssize, spoctrl, svctrl, shctrl;
+ u32 vubase, vvbase;
+ u32 vovrclk;
+
+ if (set->scaled_width==0 || set->scaled_height==0)
+ return -EINVAL;
+
+ /* read registers which have reserved bits
+ * so we can write them back as-is. */
+ vovrclk = readl(VOVRCLK);
+ vsctrl = readl(VSCTRL);
+ vscadr = readl(VSCADR);
+ vubase = readl(VUBASE);
+ vvbase = readl(VVBASE);
+
+ spoctrl = readl(SPOCTRL);
+ sssize = readl(SSSIZE);
+
+
+ vbbase = Vbbase_Glalpha(set->alpha);
+
+ vsctrl &= ~( FMsk(VSCTRL_VSWIDTH) |
+ FMsk(VSCTRL_VSHEIGHT) |
+ FMsk(VSCTRL_VPIXFMT) |
+ VSCTRL_GAMMA_EN | VSCTRL_CSC_EN |
+ VSCTRL_COSITED );
+ vsctrl |= Vsctrl_Width(set->width) | Vsctrl_Height(set->height) |
+ VSCTRL_CSC_EN;
+
+ vscadr &= ~(VSCADR_STR_EN | VSCADR_COLKEY_EN | VSCADR_COLKEYSRC |
+ FMsk(VSCADR_BLEND_M) | FMsk(VSCADR_BLEND_POS) |
+ FMsk(VSCADR_VBASE_ADR) );
+ vubase &= ~(VUBASE_UVHALFSTR | FMsk(VUBASE_UBASE_ADR));
+ vvbase &= ~(FMsk(VVBASE_VBASE_ADR));
+
+ switch (set->fmt)
+ {
+ case MBXFB_FMT_YUV12:
+ vsctrl |= VSCTRL_VPIXFMT_YUV12;
+
+ set->Y_stride = ((set->width) + 0xf ) & ~0xf;
+
+ break;
+ case MBXFB_FMT_UY0VY1:
+ vsctrl |= VSCTRL_VPIXFMT_UY0VY1;
+ set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
+ break;
+ case MBXFB_FMT_VY0UY1:
+ vsctrl |= VSCTRL_VPIXFMT_VY0UY1;
+ set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
+ break;
+ case MBXFB_FMT_Y0UY1V:
+ vsctrl |= VSCTRL_VPIXFMT_Y0UY1V;
+ set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
+ break;
+ case MBXFB_FMT_Y0VY1U:
+ vsctrl |= VSCTRL_VPIXFMT_Y0VY1U;
+ set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* VSCTRL has the bits which sets the Video Pixel Format.
+ * When passing from a packed to planar format,
+ * if we write VSCTRL first, VVBASE and VUBASE would
+ * be zero if we would not set them here. (And then,
+ * the chips hangs and only a reset seems to fix it).
+ *
+ * If course, the values calculated here have no meaning
+ * for packed formats.
+ */
+ set->UV_stride = ((set->width/2) + 0x7 ) & ~0x7;
+ set->U_offset = set->height * set->Y_stride;
+ set->V_offset = set->U_offset +
+ set->height * set->UV_stride;
+ vubase |= Vubase_Ubase_Adr(
+ (0x60000 + set->mem_offset + set->U_offset)>>3);
+ vvbase |= Vvbase_Vbase_Adr(
+ (0x60000 + set->mem_offset + set->V_offset)>>3);
+
+
+ vscadr |= VSCADR_BLEND_VID | VSCADR_BLEND_GLOB |
+ Vscadr_Vbase_Adr((0x60000 + set->mem_offset)>>4);
+
+ if (set->enable)
+ vscadr |= VSCADR_STR_EN;
+
+
+ vsadr = Vsadr_Srcstride((set->Y_stride)/16-1) |
+ Vsadr_Xstart(set->x) | Vsadr_Ystart(set->y);
+
+ sssize &= ~(FMsk(SSSIZE_SC_WIDTH) | FMsk(SSSIZE_SC_HEIGHT));
+ sssize = Sssize_Sc_Width(set->scaled_width-1) |
+ Sssize_Sc_Height(set->scaled_height-1);
+
+ spoctrl &= ~(SPOCTRL_H_SC_BP | SPOCTRL_V_SC_BP |
+ SPOCTRL_HV_SC_OR | SPOCTRL_VS_UR_C |
+ FMsk(SPOCTRL_VORDER) | FMsk(SPOCTRL_VPITCH));
+ spoctrl = Spoctrl_Vpitch((set->height<<11)/set->scaled_height)
+ | SPOCTRL_VORDER_2TAP;
+
+ /* Bypass horiz/vert scaler when same size */
+ if (set->scaled_width == set->width)
+ spoctrl |= SPOCTRL_H_SC_BP;
+ if (set->scaled_height == set->height)
+ spoctrl |= SPOCTRL_V_SC_BP;
+
+ svctrl = Svctrl_Initial1(1<<10) | Svctrl_Initial2(1<<10);
+
+ shctrl = Shctrl_Hinitial(4<<11)
+ | Shctrl_Hpitch((set->width<<11)/set->scaled_width);
+
+ /* Video plane registers */
+ write_reg(vsctrl, VSCTRL);
+ write_reg(vbbase, VBBASE);
+ write_reg(vscadr, VSCADR);
+ write_reg(vubase, VUBASE);
+ write_reg(vvbase, VVBASE);
+ write_reg(vsadr, VSADR);
+
+ /* Video scaler registers */
+ write_reg(sssize, SSSIZE);
+ write_reg(spoctrl, SPOCTRL);
+ write_reg(svctrl, SVCTRL);
+ write_reg(shctrl, SHCTRL);
+
+ /* RAPH: Using those coefficients, the scaled
+ * image is quite blurry. I dont know how
+ * to improve them ; The chip documentation
+ * was not helpful.. */
+ write_reg(0x21212121, VSCOEFF0);
+ write_reg(0x21212121, VSCOEFF1);
+ write_reg(0x21212121, VSCOEFF2);
+ write_reg(0x21212121, VSCOEFF3);
+ write_reg(0x21212121, VSCOEFF4);
+ write_reg(0x00000000, HSCOEFF0);
+ write_reg(0x00000000, HSCOEFF1);
+ write_reg(0x00000000, HSCOEFF2);
+ write_reg(0x03020201, HSCOEFF3);
+ write_reg(0x09070604, HSCOEFF4);
+ write_reg(0x0f0e0c0a, HSCOEFF5);
+ write_reg(0x15141211, HSCOEFF6);
+ write_reg(0x19181716, HSCOEFF7);
+ write_reg(0x00000019, HSCOEFF8);
+
+ /* Clock */
+ if (set->enable)
+ vovrclk |= 1;
+ else
+ vovrclk &= ~1;
+
+ write_reg(vovrclk, VOVRCLK);
+
+ return 0;
+}
+
+static int mbxfb_ioctl(struct fb_info *info, unsigned int cmd,
+ unsigned long arg)
+{
+ struct mbxfb_overlaySetup setup;
+ int res;
+
+ if (cmd == MBXFB_IOCX_OVERLAY)
+ {
+ if (copy_from_user(&setup, (void __user*)arg,
+ sizeof(struct mbxfb_overlaySetup)))
+ return -EFAULT;
+
+ res = mbxfb_setupOverlay(&setup);
+ if (res)
+ return res;
+
+ if (copy_to_user((void __user*)arg, &setup,
+ sizeof(struct mbxfb_overlaySetup)))
+ return -EFAULT;
+
+ return 0;
+ }
+ return -EINVAL;
+}
+