Currently the fsl,*lbc devices support 8 banks (ie OR and BR registers).
This is adequate for most pq2 and pq3 processors, but not the MPC8280 which
has 12 banks.
Signed-Off-By: Mark Ware <mware@elphinstone.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- struct fsl_lbc_bank bank[8];
- u8 res0[0x28];
+ struct fsl_lbc_bank bank[12];
+ u8 res0[0x8];
__be32 mar; /**< UPM Address Register */
u8 res1[0x4];
__be32 mamr; /**< UPMA Mode Register */
__be32 mar; /**< UPM Address Register */
u8 res1[0x4];
__be32 mamr; /**< UPMA Mode Register */