Also constrain the register class for branches.
This fixes rdar://problem/
18181496.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216804
91177308-0d34-0410-b5e6-
96231b3b80d8
// Issue the call.
MachineInstrBuilder MIB;
if (CM == CodeModel::Small) {
// Issue the call.
MachineInstrBuilder MIB;
if (CM == CodeModel::Small) {
- unsigned CallOpc = Addr.getReg() ? AArch64::BLR : AArch64::BL;
- MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
+ const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
+ MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
if (SymName)
MIB.addExternalSymbol(SymName, 0);
else if (Addr.getGlobalValue())
MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
if (SymName)
MIB.addExternalSymbol(SymName, 0);
else if (Addr.getGlobalValue())
MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
- else if (Addr.getReg())
- MIB.addReg(Addr.getReg());
- else
+ else if (Addr.getReg()) {
+ unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);
+ MIB.addReg(Reg);
+ } else
return false;
} else {
unsigned CallReg = 0;
return false;
} else {
unsigned CallReg = 0;
if (!CallReg)
return false;
if (!CallReg)
return false;
- MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
- TII.get(AArch64::BLR)).addReg(CallReg);
+ const MCInstrDesc &II = TII.get(AArch64::BLR);
+ CallReg = constrainOperandRegClass(II, CallReg, 0);
+ MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
}
// Add implicit physical register uses to the call.
}
// Add implicit physical register uses to the call.
; CHECK-LABEL: call_arguments9
ret void
}
; CHECK-LABEL: call_arguments9
ret void
}
+
+; Test that we use the correct register class for the branch.
+define void @call_blr(i64 %Fn, i1 %c) {
+; CHECK-LABEL: call_blr
+; CHECK: blr
+ br i1 %c, label %bb1, label %bb2
+bb1:
+ %1 = inttoptr i64 %Fn to void (i64)*
+ br label %bb2
+bb2:
+ %2 = phi void (i64)* [ %1, %bb1 ], [ undef, %0 ]
+ call void %2(i64 1)
+ ret void
+}
+