mach-imx directly references to the irq field in
struct irq_data, and uses this to directly poke hardware register.
But irq is the *virtual* irq number, something that has nothing
to do with the actual HW irq (stored in the hwirq field). And once
we put the stacked domain code in action, the whole thing explodes,
as these two values are *very* different.
Just replacing all instances of irq with hwirq fixes the issue.
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
- unsigned int idx = d->irq / 32 - 1;
+ unsigned int idx = d->hwirq / 32 - 1;
u32 mask;
/* Sanity check for SPI irq */
u32 mask;
/* Sanity check for SPI irq */
- mask = 1 << d->irq % 32;
+ mask = 1 << d->hwirq % 32;
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx] & ~mask;
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx] & ~mask;
u32 val;
/* Sanity check for SPI irq */
u32 val;
/* Sanity check for SPI irq */
- reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+ reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
val = readl_relaxed(reg);
val = readl_relaxed(reg);
- val &= ~(1 << d->irq % 32);
+ val &= ~(1 << d->hwirq % 32);
writel_relaxed(val, reg);
}
writel_relaxed(val, reg);
}
u32 val;
/* Sanity check for SPI irq */
u32 val;
/* Sanity check for SPI irq */
- reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+ reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
val = readl_relaxed(reg);
val = readl_relaxed(reg);
- val |= 1 << (d->irq % 32);
+ val |= 1 << (d->hwirq % 32);
writel_relaxed(val, reg);
}
writel_relaxed(val, reg);
}