by morphing the 'and' to its recording form 'andS'.
This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.
I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113839
91177308-0d34-0410-b5e6-
96231b3b80d8
SrcReg = MI->getOperand(0).getReg();
CmpValue = MI->getOperand(1).getImm();
return true;
SrcReg = MI->getOperand(0).getReg();
CmpValue = MI->getOperand(1).getImm();
return true;
+ case ARM::TSTri: {
+ if (MI->getParent()->begin() == MachineBasicBlock::const_iterator(MI))
+ return false;
+ const MachineInstr *AND = llvm::prior(MI);
+ if (AND->getOpcode() != ARM::ANDri)
+ return false;
+ if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
+ MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
+ SrcReg = AND->getOperand(0).getReg();
+ CmpValue = 0;
+ return true;
+ }
+ }
switch (MI->getOpcode()) {
default: break;
case ARM::ADDri:
switch (MI->getOpcode()) {
default: break;
case ARM::ADDri:
+ case ARM::ANDri:
+ case ARM::t2ANDri:
case ARM::SUBri:
case ARM::t2ADDri:
case ARM::t2SUBri:
case ARM::SUBri:
case ARM::t2ADDri:
case ARM::t2SUBri: