Generalization of Nate Begeman's patch!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502
91177308-0d34-0410-b5e6-
96231b3b80d8
return (uint32_t)(~N->getZExtValue()) < 255;
}], imm_comp_XFORM>;
return (uint32_t)(~N->getZExtValue()) < 255;
}], imm_comp_XFORM>;
+def lo5AllOne : PatLeaf<(i32 imm), [{
+ // Returns true if all low 5-bits are 1.
+ return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
+}]>;
+
// Define Thumb2 specific addressing modes.
// t2addrmode_imm12 := reg + imm12
// Define Thumb2 specific addressing modes.
// t2addrmode_imm12 := reg + imm12
defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
+// (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
+def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
+ (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
+
let Uses = [CPSR] in {
def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
"rrx", "\t$Rd, $Rm",
let Uses = [CPSR] in {
def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
"rrx", "\t$Rd, $Rm",
; CHECK: ror
define i32 @f2(i32 %v, i32 %nbits) {
entry:
; CHECK: ror
define i32 @f2(i32 %v, i32 %nbits) {
entry:
- %shr = lshr i32 %v, %nbits
- %sub = sub i32 32, %nbits
+ %and = and i32 %nbits, 31
+ %shr = lshr i32 %v, %and
+ %sub = sub i32 32, %and
%shl = shl i32 %v, %sub
%or = or i32 %shl, %shr
ret i32 %or
%shl = shl i32 %v, %sub
%or = or i32 %shl, %shr
ret i32 %or