+ }
+
+ std::vector<unsigned> Defs;
+ // We consider all Instructions as bundled because algorithm that handle
+ // const read port limitations inside an IG is still valid with single
+ // instructions.
+ std::vector<MachineInstr *> Bundle;
+
+ if (I->isBundle()) {
+ unsigned BundleSize = I->getBundleSize();
+ for (unsigned i = 0; i < BundleSize; i++) {
+ I = llvm::next(I);
+ Bundle.push_back(I);
+ }
+ } else if (TII->isALUInstr(I->getOpcode())){
+ Bundle.push_back(I);
+ } else if (isControlFlow(*I)) {
+ RegToConstIndex.clear();
+ I = llvm::next(I);
+ continue;
+ } else {
+ MachineInstr &MI = *I;
+ for (MachineInstr::mop_iterator MOp = MI.operands_begin(),
+ MOpE = MI.operands_end(); MOp != MOpE; ++MOp) {
+ MachineOperand &MO = *MOp;
+ if (!MO.isReg())
+ continue;
+ if (MO.isDef()) {
+ Defs.push_back(MO.getReg());
+ } else {
+ // Either a TEX or an Export inst, prevent from erasing def of used
+ // operand
+ RegToConstIndex.erase(MO.getReg());
+ for (MCSubRegIterator SR(MO.getReg(), &TII->getRegisterInfo());
+ SR.isValid(); ++SR) {
+ RegToConstIndex.erase(*SR);
+ }
+ }
+ }
+ }
+
+
+ R600Operands::Ops OpTable[3][2] = {
+ {R600Operands::SRC0, R600Operands::SRC0_SEL},
+ {R600Operands::SRC1, R600Operands::SRC1_SEL},
+ {R600Operands::SRC2, R600Operands::SRC2_SEL},
+ };
+
+ for(std::vector<MachineInstr *>::iterator It = Bundle.begin(),
+ ItE = Bundle.end(); It != ItE; ++It) {
+ MachineInstr *MI = *It;
+ if (TII->isPredicated(MI)) {
+ // We don't want to erase previous assignment
+ RegToConstIndex.erase(MI->getOperand(0).getReg());
+ } else {
+ int WriteIDX = TII->getOperandIdx(MI->getOpcode(), R600Operands::WRITE);
+ if (WriteIDX < 0 || MI->getOperand(WriteIDX).getImm())
+ Defs.push_back(MI->getOperand(0).getReg());
+ }
+ }
+
+ ConstPairs CP = {0,0};
+ for (unsigned SrcOp = 0; SrcOp < 3; SrcOp++) {
+ for(std::vector<MachineInstr *>::iterator It = Bundle.begin(),
+ ItE = Bundle.end(); It != ItE; ++It) {
+ MachineInstr *MI = *It;
+ int SrcIdx = TII->getOperandIdx(MI->getOpcode(), OpTable[SrcOp][0]);
+ if (SrcIdx < 0)
+ continue;
+ MachineOperand &MO = MI->getOperand(SrcIdx);
+ DenseMap<unsigned, MachineInstr *>::iterator SrcMI =
+ RegToConstIndex.find(MO.getReg());
+ if (SrcMI != RegToConstIndex.end()) {
+ MachineInstr *CstMov = SrcMI->second;
+ int ConstMovSel =
+ TII->getOperandIdx(CstMov->getOpcode(), R600Operands::SRC0_SEL);
+ unsigned ConstIndex = CstMov->getOperand(ConstMovSel).getImm();
+ if (canFoldInBundle(CP, ConstIndex)) {
+ TII->setImmOperand(MI, OpTable[SrcOp][1], ConstIndex);
+ MI->getOperand(SrcIdx).setReg(AMDGPU::ALU_CONST);
+ } else {
+ RegToConstIndex.erase(SrcMI);
+ }
+ }
+ }
+ }
+
+ for (std::vector<unsigned>::iterator It = Defs.begin(), ItE = Defs.end();
+ It != ItE; ++It) {
+ DenseMap<unsigned, MachineInstr *>::iterator SrcMI =
+ RegToConstIndex.find(*It);
+ if (SrcMI != RegToConstIndex.end()) {
+ SrcMI->second->eraseFromParent();
+ RegToConstIndex.erase(SrcMI);
+ }
+ }
+ I = llvm::next(I);
+ }
+
+ if (MBB.succ_empty()) {
+ for (DenseMap<unsigned, MachineInstr *>::iterator
+ DI = RegToConstIndex.begin(), DE = RegToConstIndex.end();
+ DI != DE; ++DI) {
+ DI->second->eraseFromParent();
+ }