-#define SCLK_GPU_CORE 64
-#define SCLK_SPI0 65
-#define SCLK_SPI1 66
-#define SCLK_SPI2 68
-#define SCLK_SPI3 69
-#define SCLK_SPI4 70
-#define SCLK_SDMMC 71
-#define SCLK_SDIO0 72
-#define SCLK_EMMC 73
-#define SCLK_TSADC 74
-#define SCLK_SARADC 75
-#define SCLK_NANDC0 76
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_UART3 80
-#define SCLK_UART4 81
-#define SCLK_SPDIF_8CH 82
-#define SCLK_I2S0_8CH 83
-#define SCLK_I2S1_8CH 84
-#define SCLK_I2S2_8CH 85
-#define SCLK_TIMER00 86
-#define SCLK_TIMER01 87
-#define SCLK_TIMER02 88
-#define SCLK_TIMER03 89
-#define SCLK_TIMER04 90
-#define SCLK_TIMER05 91
-#define SCLK_TIMER06 92
-#define SCLK_TIMER07 93
-#define SCLK_TIMER08 94
-#define SCLK_TIMER09 95
-#define SCLK_TIMER10 96
-#define SCLK_TIMER11 97
-#define SCLK_HSICPHY480M 98
-#define SCLK_HSICPHY12M 99
-#define SCLK_MACREF 100
-#define SCLK_VOPB_PWM 101
-#define SCLK_VOPL_PWM 102
-#define SCLK_EDP_24M 104
-#define SCLK_EDP 105
-#define SCLK_RGA 106
-#define SCLK_ISP 107
-#define SCLK_HDCP 108
-#define SCLK_HDMI_HDCP 109
-#define SCLK_HDMI_CEC 110
-#define SCLK_HEVC_CABAC 111
-#define SCLK_HEVC_CORE 112
-#define SCLK_I2S_8CH_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO0_DRV 115
-#define SCLK_SDIO1_DRV 116
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO0_SAMPLE 119
-#define SCLK_SDIO1_SAMPLE 120
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_USBPHY480M 122
-#define SCLK_PVTM_CORE_L 123
-#define SCLK_PVTM_CORE_B 124
-#define SCLK_PVTM_GPU 125
-#define SCLK_PVTM_PMU 126
-#define SCLK_SFC 127
-#define SCLK_MAC_RX 128
-#define SCLK_MAC_TX 129
-#define SCLK_MAC 130
-#define SCLK_MACREF_OUT 131
-#define SCLK_USB2_PHY0_REF 132
-#define SCLK_USB2_PHY1_REF 133
-#define SCLK_USB3_OTG0_REF 134
-#define SCLK_USB3_OTG1_REF 135
-#define SCLK_USB3_OTG0_SUSPEND 136
-#define SCLK_USB3_OTG1_SUSPEND 137
-#define SCLK_CRYPTO 138
-#define SCLK_CRYPTO1 139
-
-#define DCLK_VOPB 170
-#define DCLK_VOPL 171
-#define MCLK_CRYPTO 172
-#define MCLK_CRYPTO1 173
+#define SCLK_I2C1 65
+#define SCLK_I2C2 66
+#define SCLK_I2C3 67
+#define SCLK_I2C5 68
+#define SCLK_I2C6 69
+#define SCLK_I2C7 70
+#define SCLK_SPI0 71
+#define SCLK_SPI1 72
+#define SCLK_SPI2 73
+#define SCLK_SPI4 74
+#define SCLK_SPI5 75
+#define SCLK_SDMMC 76
+#define SCLK_SDIO 77
+#define SCLK_EMMC 78
+#define SCLK_TSADC 79
+#define SCLK_SARADC 80
+#define SCLK_UART0 81
+#define SCLK_UART1 82
+#define SCLK_UART2 83
+#define SCLK_UART3 84
+#define SCLK_SPDIF_8CH 85
+#define SCLK_I2S0_8CH 86
+#define SCLK_I2S1_8CH 87
+#define SCLK_I2S2_8CH 88
+#define SCLK_I2S_8CH_OUT 89
+#define SCLK_TIMER00 90
+#define SCLK_TIMER01 91
+#define SCLK_TIMER02 92
+#define SCLK_TIMER03 93
+#define SCLK_TIMER04 94
+#define SCLK_TIMER05 95
+#define SCLK_TIMER06 96
+#define SCLK_TIMER07 97
+#define SCLK_TIMER08 98
+#define SCLK_TIMER09 99
+#define SCLK_TIMER10 100
+#define SCLK_TIMER11 101
+#define SCLK_MACREF 102
+#define SCLK_MAC_RX 103
+#define SCLK_MAC_TX 104
+#define SCLK_MAC 105
+#define SCLK_MACREF_OUT 106
+#define SCLK_VOP0_PWM 107
+#define SCLK_VOP1_PWM 108
+#define SCLK_RGA 109
+#define SCLK_ISP0 110
+#define SCLK_ISP1 111
+#define SCLK_HDMI_CEC 112
+#define SCLK_HDMI_SFR 113
+#define SCLK_DP_CORE_SRC 114
+#define SCLK_PVTM_CORE_L 115
+#define SCLK_PVTM_CORE_B 116
+#define SCLK_PVTM_GPU 117
+#define SCLK_PVTM_DDR 118
+#define SCLK_MIPIDPHY_REF 119
+#define SCLK_MIPIDPHY_CFG 120
+#define SCLK_HSICPHY 121
+#define SCLK_USBPHY480M 122
+#define SCLK_USB2PHY0_REF 123
+#define SCLK_USB2PHY1_REF 124
+#define SCLK_UPHY0_TCPDPHY_REF 125
+#define SCLK_UPHY0_TCPDCORE 126
+#define SCLK_UPHY1_TCPDPHY_REF 127
+#define SCLK_UPHY1_TCPDCORE 128
+#define SCLK_USB3OTG0_REF 129
+#define SCLK_USB3OTG1_REF 130
+#define SCLK_USB3OTG0_SUSPEND 131
+#define SCLK_USB3OTG1_SUSPEND 132
+#define SCLK_CRYPTO0 133
+#define SCLK_CRYPTO1 134
+#define SCLK_CCI_TRACE 135
+#define SCLK_CS 136
+#define SCLK_CIF_OUT 137
+#define SCLK_PCIEPHY_REF 138
+#define SCLK_PCIE_CORE 139
+#define SCLK_MO_PERILP 140
+#define SCLK_M0_PERILP_DEC 141
+#define SCLK_CM0S 142
+#define SCLK_DBG_NOC 143
+#define SCLK_DBG_PD_CORE_B 144
+#define SCLK_DBG_PD_CORE_L 145
+#define SCLK_DFIMON0_TIMER 146
+#define SCLK_DFIMON1_TIMER 147
+#define SCLK_INTMEM0 148
+#define SCLK_INTMEM1 149
+#define SCLK_INTMEM2 150
+#define SCLK_INTMEM3 151
+#define SCLK_INTMEM4 152
+#define SCLK_INTMEM5 153
+
+#define DCLK_VOP0 170
+#define DCLK_VOP1 171