- const MachineInstr *MI = MO.getParent();
- unsigned OpNo = (&MO - &MI->getOperand(0));
-
- // Find the SlotIndex being read.
- SlotIndex Idx;
- if (MI->isPHI()) {
- assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
- // PHI operands are paired: (Reg, PredMBB).
- // Extend the live range to be live-out from PredMBB.
- Idx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
- } else {
- // This is a normal instruction.
- Idx = Indexes->getInstructionIndex(MI).getRegSlot();
- // Check for early-clobber redefs.
- unsigned DefIdx;
- if (MO.isDef()) {
- if (MO.isEarlyClobber())
- Idx = Idx.getRegSlot(true);
- } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
- // FIXME: This would be a lot easier if tied early-clobber uses also
- // had an early-clobber flag.
- if (MI->getOperand(DefIdx).isEarlyClobber())
- Idx = Idx.getRegSlot(true);
+ SlotIndex Idx = getUseIndex(*Indexes, MO);
+ extend(LR, Idx, Reg, MainLiveOutData);
+ }
+}
+
+
+void LiveRangeCalc::extendToUses(LiveInterval &LI) {
+ assert(MRI && Indexes && "call reset() first");
+
+ const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
+ SmallVector<LiveOutData,2> LiveOuts;
+ unsigned NumSubRanges = 0;
+ for (LiveInterval::subrange_iterator S = LI.subrange_begin(),
+ SE = LI.subrange_end(); S != SE; ++S, ++NumSubRanges) {
+ LiveOuts.push_back(LiveOutData());
+ LiveOuts.back().reset(MF->getNumBlockIDs());
+ }
+
+ // Visit all operands that read Reg. This may include partial defs.
+ unsigned Reg = LI.reg;
+ for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
+ // Clear all kill flags. They will be reinserted after register allocation
+ // by LiveIntervalAnalysis::addKillFlags().
+ if (MO.isUse())
+ MO.setIsKill(false);
+ if (!MO.readsReg())
+ continue;
+ SlotIndex Idx = getUseIndex(*Indexes, MO);
+ unsigned SubReg = MO.getSubReg();
+ if (MO.isUse() && (LI.hasSubRanges() || SubReg != 0)) {
+ unsigned Mask = SubReg != 0
+ ? TRI.getSubRegIndexLaneMask(SubReg)
+ : Mask = MRI->getMaxLaneMaskForVReg(Reg);
+
+ // If this is the first time we see a subregister def/use. Initialize
+ // subranges by creating a copy of the main range.
+ if (!LI.hasSubRanges()) {
+ unsigned ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
+ LI.createSubRangeFrom(*Alloc, ClassMask, LI);
+ LiveOuts.insert(LiveOuts.begin(), LiveOutData());
+ LiveOuts.front().reset(MF->getNumBlockIDs());
+ ++NumSubRanges;
+ }
+ unsigned SubRangeIdx = 0;
+ for (LiveInterval::subrange_iterator S = LI.subrange_begin(),
+ SE = LI.subrange_end(); S != SE; ++S, ++SubRangeIdx) {
+ // A Mask for subregs common to the existing subrange and current def.
+ unsigned Common = S->LaneMask & Mask;
+ if (Common == 0)
+ continue;
+ // A Mask for subregs covered by the subrange but not the current def.
+ unsigned LRest = S->LaneMask & ~Mask;
+ LiveInterval::SubRange *CommonRange;
+ unsigned CommonRangeIdx;
+ if (LRest != 0) {
+ // Split current subrange into Common and LRest ranges.
+ S->LaneMask = LRest;
+ CommonRange = LI.createSubRangeFrom(*Alloc, Common, *S);
+ CommonRangeIdx = 0;
+ LiveOuts.insert(LiveOuts.begin(), LiveOutData());
+ LiveOuts.front().reset(MF->getNumBlockIDs());
+ ++NumSubRanges;
+ ++SubRangeIdx;
+ } else {
+ // The subrange and current def lanemasks match completely.
+ assert(Common == S->LaneMask);
+ CommonRange = &*S;
+ CommonRangeIdx = SubRangeIdx;
+ }
+ extend(*CommonRange, Idx, Reg, LiveOuts[CommonRangeIdx]);
+ Mask &= ~Common;