pressure, not decreases register pressure. Fix problem where we accidentally
swapped the operands of SHLD, which caused fourinarow to fail. This fixes
fourinarow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19697
91177308-0d34-0410-b5e6-
96231b3b80d8
} else if (RegSize != 8) {
unsigned AReg, BReg;
if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
} else if (RegSize != 8) {
unsigned AReg, BReg;
if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
- AReg = SelectExpr(ShrVal);
BReg = SelectExpr(ShlVal);
BReg = SelectExpr(ShlVal);
+ AReg = SelectExpr(ShrVal);
- BReg = SelectExpr(ShlVal);
AReg = SelectExpr(ShrVal);
AReg = SelectExpr(ShrVal);
+ BReg = SelectExpr(ShlVal);
}
unsigned ShAmt = SelectExpr(ShrAmt);
BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
}
unsigned ShAmt = SelectExpr(ShrAmt);
BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
} else if (RegSize != 8) {
unsigned AReg, BReg;
if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
} else if (RegSize != 8) {
unsigned AReg, BReg;
if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
- AReg = SelectExpr(ShrVal);
- BReg = SelectExpr(ShlVal);
+ AReg = SelectExpr(ShlVal);
+ BReg = SelectExpr(ShrVal);
- BReg = SelectExpr(ShlVal);
- AReg = SelectExpr(ShrVal);
+ BReg = SelectExpr(ShrVal);
+ AReg = SelectExpr(ShlVal);
}
unsigned ShAmt = SelectExpr(ShlAmt);
BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
}
unsigned ShAmt = SelectExpr(ShlAmt);
BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
} else if (RegSize != 8) {
unsigned AReg, BReg;
if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
} else if (RegSize != 8) {
unsigned AReg, BReg;
if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
- AReg = SelectExpr(ShrVal);
BReg = SelectExpr(ShlVal);
BReg = SelectExpr(ShlVal);
+ AReg = SelectExpr(ShrVal);
- BReg = SelectExpr(ShlVal);
AReg = SelectExpr(ShrVal);
AReg = SelectExpr(ShrVal);
+ BReg = SelectExpr(ShlVal);
}
unsigned Opc = RegSize == 16 ? X86::SHRD16rri8 : X86::SHRD32rri8;
BuildMI(BB, Opc, 3, DestReg).addReg(AReg).addReg(BReg)
}
unsigned Opc = RegSize == 16 ? X86::SHRD16rri8 : X86::SHRD32rri8;
BuildMI(BB, Opc, 3, DestReg).addReg(AReg).addReg(BReg)