+
+; CHECK-LABEL: test14
+; CHECK: vpcmp
+; CHECK-NOT: vpcmp
+; CHECK: vmovdqu32 {{.*}}{%k1} {z}
+; CHECK: ret
+define <16 x i32> @test14(<16 x i32>%a, <16 x i32>%b) {
+ %sub_r = sub <16 x i32> %a, %b
+ %cmp.i2.i = icmp sgt <16 x i32> %sub_r, %a
+ %sext.i3.i = sext <16 x i1> %cmp.i2.i to <16 x i32>
+ %mask = icmp eq <16 x i32> %sext.i3.i, zeroinitializer
+ %res = select <16 x i1> %mask, <16 x i32> zeroinitializer, <16 x i32> %sub_r
+ ret <16 x i32>%res
+}
+
+; CHECK-LABEL: test15
+; CHECK: vpcmpgtq
+; CHECK-NOT: vpcmp
+; CHECK: vmovdqu64 {{.*}}{%k1} {z}
+; CHECK: ret
+define <8 x i64> @test15(<8 x i64>%a, <8 x i64>%b) {
+ %sub_r = sub <8 x i64> %a, %b
+ %cmp.i2.i = icmp sgt <8 x i64> %sub_r, %a
+ %sext.i3.i = sext <8 x i1> %cmp.i2.i to <8 x i64>
+ %mask = icmp eq <8 x i64> %sext.i3.i, zeroinitializer
+ %res = select <8 x i1> %mask, <8 x i64> zeroinitializer, <8 x i64> %sub_r
+ ret <8 x i64>%res
+}
+