if (TID->Flags & M_CLOBBERS_PRED)
BBI.ClobbersPred = true;
if (TID->Flags & M_CLOBBERS_PRED)
BBI.ClobbersPred = true;
- if (!I->isPredicable()) {
+ if ((TID->Flags & M_PREDICABLE) == 0) {
BBI.IsUnpredicable = true;
return;
}
BBI.IsUnpredicable = true;
return;
}
while (TT != BBI.TrueBB->end() && FT != BBI.FalseBB->end()) {
if (TT->isIdenticalTo(FT))
Dups.push_back(TT); // Will erase these later.
while (TT != BBI.TrueBB->end() && FT != BBI.FalseBB->end()) {
if (TT->isIdenticalTo(FT))
Dups.push_back(TT); // Will erase these later.
- else if (!TT->isPredicable() && !FT->isPredicable())
+ else if ((TT->getInstrDescriptor()->Flags & M_PREDICABLE) == 0 ||
+ (FT->getInstrDescriptor()->Flags & M_PREDICABLE) == 0)
return false; // Can't if-convert. Abort!
++TT;
++FT;
return false; // Can't if-convert. Abort!
++TT;
++FT;
// One of the two pathes have more terminators, make sure they are
// all predicable.
while (TT != BBI.TrueBB->end()) {
// One of the two pathes have more terminators, make sure they are
// all predicable.
while (TT != BBI.TrueBB->end()) {
- if (!TT->isPredicable()) {
+ if ((TT->getInstrDescriptor()->Flags & M_PREDICABLE) == 0)
return false; // Can't if-convert. Abort!
return false; // Can't if-convert. Abort!
++TT;
}
while (FT != BBI.FalseBB->end()) {
++TT;
}
while (FT != BBI.FalseBB->end()) {
- if (!FT->isPredicable()) {
+ if ((FT->getInstrDescriptor()->Flags & M_PREDICABLE) == 0)
return false; // Can't if-convert. Abort!
return false; // Can't if-convert. Abort!
-bool MachineInstr::isPredicable() const {
- return TID->Flags & M_PREDICABLE;
-}
-
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
/// the specific register or -1 if it is not found. It further tightening
/// the search criteria to a use that kills the register if isKill is true.
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
/// the specific register or -1 if it is not found. It further tightening
/// the search criteria to a use that kills the register if isKill is true.