instruction scheduling (this is off by default).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8553
91177308-0d34-0410-b5e6-
96231b3b80d8
SchedDebugLevel_t SchedDebugLevel;
SchedDebugLevel_t SchedDebugLevel;
+static cl::opt<bool> EnableFillingDelaySlots("sched-fill-delay-slots",
+ cl::desc("Fill branch delay slots during local scheduling"));
+
static cl::opt<SchedDebugLevel_t, true>
SDL_opt("dsched", cl::Hidden, cl::location(SchedDebugLevel),
cl::desc("enable instruction scheduling debugging information"),
static cl::opt<SchedDebugLevel_t, true>
SDL_opt("dsched", cl::Hidden, cl::location(SchedDebugLevel),
cl::desc("enable instruction scheduling debugging information"),
std::vector<SchedGraphNode*> delayNodeVec;
const MachineInstr* brInstr = NULL;
std::vector<SchedGraphNode*> delayNodeVec;
const MachineInstr* brInstr = NULL;
- if (termInstr->getOpcode() != Instruction::Ret)
+ if (EnableFillingDelaySlots &&
+ termInstr->getOpcode() != Instruction::Ret)
{
// To find instructions that need delay slots without searching the full
// machine code, we assume that the only delayed instructions are CALLs
{
// To find instructions that need delay slots without searching the full
// machine code, we assume that the only delayed instructions are CALLs
// Also mark delay slots for other delayed instructions to hold NOPs.
// Simply passing in an empty delayNodeVec will have this effect.
// Also mark delay slots for other delayed instructions to hold NOPs.
// Simply passing in an empty delayNodeVec will have this effect.
+ // If brInstr is not handled above (EnableFillingDelaySlots == false),
+ // brInstr will be NULL so this will handle the branch instrs. as well.
//
delayNodeVec.clear();
for (unsigned i=0; i < MBB.size(); ++i)
//
delayNodeVec.clear();
for (unsigned i=0; i < MBB.size(); ++i)
SchedDebugLevel_t SchedDebugLevel;
SchedDebugLevel_t SchedDebugLevel;
+static cl::opt<bool> EnableFillingDelaySlots("sched-fill-delay-slots",
+ cl::desc("Fill branch delay slots during local scheduling"));
+
static cl::opt<SchedDebugLevel_t, true>
SDL_opt("dsched", cl::Hidden, cl::location(SchedDebugLevel),
cl::desc("enable instruction scheduling debugging information"),
static cl::opt<SchedDebugLevel_t, true>
SDL_opt("dsched", cl::Hidden, cl::location(SchedDebugLevel),
cl::desc("enable instruction scheduling debugging information"),
std::vector<SchedGraphNode*> delayNodeVec;
const MachineInstr* brInstr = NULL;
std::vector<SchedGraphNode*> delayNodeVec;
const MachineInstr* brInstr = NULL;
- if (termInstr->getOpcode() != Instruction::Ret)
+ if (EnableFillingDelaySlots &&
+ termInstr->getOpcode() != Instruction::Ret)
{
// To find instructions that need delay slots without searching the full
// machine code, we assume that the only delayed instructions are CALLs
{
// To find instructions that need delay slots without searching the full
// machine code, we assume that the only delayed instructions are CALLs
// Also mark delay slots for other delayed instructions to hold NOPs.
// Simply passing in an empty delayNodeVec will have this effect.
// Also mark delay slots for other delayed instructions to hold NOPs.
// Simply passing in an empty delayNodeVec will have this effect.
+ // If brInstr is not handled above (EnableFillingDelaySlots == false),
+ // brInstr will be NULL so this will handle the branch instrs. as well.
//
delayNodeVec.clear();
for (unsigned i=0; i < MBB.size(); ++i)
//
delayNodeVec.clear();
for (unsigned i=0; i < MBB.size(); ++i)