+namespace {
+ struct LogicOp {
+ LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
+ LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
+ : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
+
+ operator bool() const { return RegSize; }
+
+ unsigned RegSize, ImmLSB, ImmSize;
+ };
+}
+
+static LogicOp interpretAndImmediate(unsigned Opcode) {
+ switch (Opcode) {
+ case SystemZ::NILL32: return LogicOp(32, 0, 16);
+ case SystemZ::NILH32: return LogicOp(32, 16, 16);
+ case SystemZ::NILL: return LogicOp(64, 0, 16);
+ case SystemZ::NILH: return LogicOp(64, 16, 16);
+ case SystemZ::NIHL: return LogicOp(64, 32, 16);
+ case SystemZ::NIHH: return LogicOp(64, 48, 16);
+ case SystemZ::NILF32: return LogicOp(32, 0, 32);
+ case SystemZ::NILF: return LogicOp(64, 0, 32);
+ case SystemZ::NIHF: return LogicOp(64, 32, 32);
+ default: return LogicOp();
+ }
+}
+
+// Used to return from convertToThreeAddress after replacing two-address
+// instruction OldMI with three-address instruction NewMI.
+static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
+ MachineInstr *NewMI,
+ LiveVariables *LV) {
+ if (LV) {
+ unsigned NumOps = OldMI->getNumOperands();
+ for (unsigned I = 1; I < NumOps; ++I) {
+ MachineOperand &Op = OldMI->getOperand(I);
+ if (Op.isReg() && Op.isKill())
+ LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
+ }
+ }
+ return NewMI;
+}
+