git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181250
91177308-0d34-0410-b5e6-
96231b3b80d8
-static cl::
-opt<bool> DisableHardwareLoops(
- "disable-hexagon-hwloops", cl::Hidden,
- cl::desc("Disable Hardware Loops for Hexagon target"));
+static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
+ cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
-static cl::
-opt<bool> DisableHexagonMISched("disable-hexagon-misched",
- cl::Hidden, cl::ZeroOrMore, cl::init(false),
- cl::desc("Disable Hexagon MI Scheduling"));
+static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
+ cl::Hidden, cl::ZeroOrMore, cl::init(false),
+ cl::desc("Disable Hexagon MI Scheduling"));
static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
- cl::Hidden, cl::ZeroOrMore, cl::init(false),
- cl::desc("Disable Hexagon CFG Optimization"));
+ cl::Hidden, cl::ZeroOrMore, cl::init(false),
+ cl::desc("Disable Hexagon CFG Optimization"));
+
/// HexagonTargetMachineModule - Note that this is used on hosts that
/// cannot link in a library unless there are references into the
/// HexagonTargetMachineModule - Note that this is used on hosts that
/// cannot link in a library unless there are references into the
}
bool HexagonPassConfig::addInstSelector() {
}
bool HexagonPassConfig::addInstSelector() {
+ const HexagonTargetMachine &TM = getHexagonTargetMachine();
+ bool NoOpt = (getOptLevel() == CodeGenOpt::None);
- if (getOptLevel() != CodeGenOpt::None)
- addPass(createHexagonRemoveExtendArgs(getHexagonTargetMachine()));
+ if (!NoOpt)
+ addPass(createHexagonRemoveExtendArgs(TM));
- addPass(createHexagonISelDag(getHexagonTargetMachine(), getOptLevel()));
+ addPass(createHexagonISelDag(TM, getOptLevel()));
- if (getOptLevel() != CodeGenOpt::None)
addPass(createHexagonPeephole());
addPass(createHexagonPeephole());
+ printAndVerify("After hexagon peephole pass");
+ }
bool HexagonPassConfig::addPreRegAlloc() {
bool HexagonPassConfig::addPreRegAlloc() {
- if (!DisableHardwareLoops && getOptLevel() != CodeGenOpt::None)
- addPass(createHexagonHardwareLoops());
+ if (getOptLevel() != CodeGenOpt::None)
+ if (!DisableHardwareLoops)
+ addPass(createHexagonHardwareLoops());
return false;
}
bool HexagonPassConfig::addPostRegAlloc() {
return false;
}
bool HexagonPassConfig::addPostRegAlloc() {
- if (!DisableHexagonCFGOpt && getOptLevel() != CodeGenOpt::None)
- addPass(createHexagonCFGOptimizer(getHexagonTargetMachine()));
- return true;
+ const HexagonTargetMachine &TM = getHexagonTargetMachine();
+ if (getOptLevel() != CodeGenOpt::None)
+ if (!DisableHexagonCFGOpt)
+ addPass(createHexagonCFGOptimizer(TM));
+ return false;
bool HexagonPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None)
addPass(&IfConverterID);
bool HexagonPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None)
addPass(&IfConverterID);
}
bool HexagonPassConfig::addPreEmitPass() {
}
bool HexagonPassConfig::addPreEmitPass() {
+ const HexagonTargetMachine &TM = getHexagonTargetMachine();
+ bool NoOpt = (getOptLevel() == CodeGenOpt::None);
- if (!DisableHardwareLoops && getOptLevel() != CodeGenOpt::None)
- addPass(createHexagonFixupHwLoops());
-
- if (getOptLevel() != CodeGenOpt::None)
addPass(createHexagonNewValueJump());
// Expand Spill code for predicate registers.
addPass(createHexagonNewValueJump());
// Expand Spill code for predicate registers.
- addPass(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
+ addPass(createHexagonExpandPredSpillCode(TM));
// Split up TFRcondsets into conditional transfers.
// Split up TFRcondsets into conditional transfers.
- addPass(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
+ addPass(createHexagonSplitTFRCondSets(TM));
- if (getOptLevel() != CodeGenOpt::None)
+ if (!NoOpt) {
+ if (!DisableHardwareLoops)
+ addPass(createHexagonFixupHwLoops());
addPass(createHexagonPacketizer());
addPass(createHexagonPacketizer());