+
+ <!-- to write:
+ MachineCSE tuned and on by default.
+ llvm.dbg.value: variable debug info for optimized code
+ MC Assembler backend is now real, does relaxation and is bitwise identical
+ with darwin assembler in huge majority of all cases.
+ new GHC calling convention
+ New half float intrinsics LangRef.html#int_fp16
+ Rewrote tblgen's type inference for backends to be more consistent and
+ diagnose more target bugs. This also allows limited support for writing
+ patterns for instructions that return multiple results, e.g. a virtual
+ register and a flag result. Stuff that used 'parallel' before should use
+ this.
+ New ARM/Thumb disassembler support in MC.
+ New SSEDomainFix pass:
+ On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a
+ register in a different domain than where it was defined. Some instructions
+ have equvivalents for different domains, like por/orps/orpd. The
+ SSEDomainFix pass tries to minimize the number of domain crossings by
+ changing between equvivalent opcodes where possible.
+ Support for the Intel AES instructions in the assembler.
+ memcpy, memmove, and memset now take address space qualified pointers + volatile.
+
+ -->
+