git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154372
91177308-0d34-0410-b5e6-
96231b3b80d8
// List of super-registers in topological order, small to large.
typedef std::vector<const CodeGenRegister*> SuperRegList;
// List of super-registers in topological order, small to large.
typedef std::vector<const CodeGenRegister*> SuperRegList;
- // Get the list of super-registers.
- // This is only valid after computeDerivedInfo has visited all registers.
+ // Get the list of super-registers. This is valid after getSubReg
+ // visits all registers during RegBank construction.
const SuperRegList &getSuperRegs() const {
assert(SubRegsComplete && "Must precompute sub-registers");
return SuperRegs;
const SuperRegList &getSuperRegs() const {
assert(SubRegsComplete && "Must precompute sub-registers");
return SuperRegs;