-//===----------------------------------------------------------------------===//
-// ALU32/PERM +
-//===----------------------------------------------------------------------===//
-
-// Combine
-// Rdd=combine(Rs, #s8)
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
- hasSideEffects = 0, validSubTargets = HasV4SubT in
-def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
- (ins IntRegs:$src1, s8Ext:$src2),
- "$dst = combine($src1, #$src2)",
- []>,
- Requires<[HasV4T]>;
-
-// Rdd=combine(#s8, Rs)
-let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
- hasSideEffects = 0, validSubTargets = HasV4SubT in
-def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
- (ins s8Ext:$src1, IntRegs:$src2),
- "$dst = combine(#$src1, $src2)",
- []>,
- Requires<[HasV4T]>;
-
-def HexagonWrapperCombineRI_V4 :
- SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
-def HexagonWrapperCombineIR_V4 :
- SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
-
-def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
- (COMBINE_rI_V4 IntRegs:$r, s8ExtPred:$i)>,
- Requires<[HasV4T]>;
-
-def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
- (COMBINE_Ir_V4 s8ExtPred:$i, IntRegs:$r)>,
- Requires<[HasV4T]>;
-
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
- hasSideEffects = 0, validSubTargets = HasV4SubT in
-def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
- (ins s8Imm:$src1, u6Ext:$src2),
- "$dst = combine(#$src1, #$src2)",
- []>,
- Requires<[HasV4T]>;
-