The SIInsertWaits pass was overwriting the first operand (gds bit) of
DS_WRITE_B32 with the second operand (value to write). This meant that
any time the value to write was stored in an odd number VGPR, the gds
bit would be set causing the instruction to write to GDS instead of LDS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188522
91177308-0d34-0410-b5e6-
96231b3b80d8
// LGKM may uses larger values
if (TSFlags & SIInstrFlags::LGKM_CNT) {
// LGKM may uses larger values
if (TSFlags & SIInstrFlags::LGKM_CNT) {
- MachineOperand &Op = MI.getOperand(0);
- if (!Op.isReg())
- Op = MI.getOperand(1);
+ const MachineOperand &Op = MI.getOperand(0);
assert(Op.isReg() && "First LGKM operand must be a register!");
unsigned Reg = Op.getReg();
assert(Op.isReg() && "First LGKM operand must be a register!");
unsigned Reg = Op.getReg();
class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
op,
(outs regClass:$vdst),
class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
op,
(outs regClass:$vdst),
- (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
- i8imm:$offset0, i8imm:$offset1),
+ (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
+ i8imm:$offset0, i8imm:$offset1, i1imm:$gds),
asm#" $vdst, $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
[]> {
let mayLoad = 1;
asm#" $vdst, $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
[]> {
let mayLoad = 1;
class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
op,
(outs),
class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
op,
(outs),
- (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
- i8imm:$offset0, i8imm:$offset1),
+ (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
+ i8imm:$offset0, i8imm:$offset1, i1imm:$gds),
asm#" $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
[]> {
let mayStore = 1;
asm#" $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
[]> {
let mayStore = 1;
def : Pat <
(local_load i64:$src0),
def : Pat <
(local_load i64:$src0),
- (i32 (DS_READ_B32 0, (EXTRACT_SUBREG $src0, sub0),
- (EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0))
+ (i32 (DS_READ_B32 (EXTRACT_SUBREG $src0, sub0),
+ (EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0, 0))
>;
def : Pat <
(local_store i32:$src1, i64:$src0),
>;
def : Pat <
(local_store i32:$src1, i64:$src0),
- (DS_WRITE_B32 0, (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0)
+ (DS_WRITE_B32 (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0, 0)
>;
/********** ================== **********/
>;
/********** ================== **********/
; SI-CHECK-NEXT: .long 32768
; EG-CHECK: LDS_WRITE
; SI-CHECK-NEXT: .long 32768
; EG-CHECK: LDS_WRITE
-; SI-CHECK: DS_WRITE_B32
+; SI-CHECK: DS_WRITE_B32 0
; GROUP_BARRIER must be the last instruction in a clause
; EG-CHECK: GROUP_BARRIER
; GROUP_BARRIER must be the last instruction in a clause
; EG-CHECK: GROUP_BARRIER
; SI-CHECK: S_BARRIER
; EG-CHECK: LDS_READ_RET
; SI-CHECK: S_BARRIER
; EG-CHECK: LDS_READ_RET
+; SI-CHECK: DS_READ_B32 VGPR{{[0-9]}}, 0
define void @local_memory(i32 addrspace(1)* %out) {
entry:
define void @local_memory(i32 addrspace(1)* %out) {
entry: