cl::desc("Debug control for aggressive anti-dep breaker"),
cl::init(0), cl::Hidden);
cl::desc("Debug control for aggressive anti-dep breaker"),
cl::init(0), cl::Hidden);
-AggressiveAntiDepState::AggressiveAntiDepState(MachineBasicBlock *BB) :
- GroupNodes(TargetRegisterInfo::FirstVirtualRegister, 0) {
- // Initialize all registers to be in their own group. Initially we
- // assign the register to the same-indexed GroupNode.
- for (unsigned i = 0; i < TargetRegisterInfo::FirstVirtualRegister; ++i)
+AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
+ MachineBasicBlock *BB) :
+ NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0) {
+
+ const unsigned BBSize = BB->size();
+ for (unsigned i = 0; i < NumTargetRegs; ++i) {
+ // Initialize all registers to be in their own group. Initially we
+ // assign the register to the same-indexed GroupNode.
-
- // Initialize the indices to indicate that no registers are live.
- std::fill(KillIndices, array_endof(KillIndices), ~0u);
- std::fill(DefIndices, array_endof(DefIndices), BB->size());
+ // Initialize the indices to indicate that no registers are live.
+ KillIndices[i] = ~0u;
+ DefIndices[i] = BBSize;
+ }
}
unsigned AggressiveAntiDepState::GetGroup(unsigned Reg)
}
unsigned AggressiveAntiDepState::GetGroup(unsigned Reg)
std::vector<unsigned> &Regs,
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
{
std::vector<unsigned> &Regs,
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
{
- for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
+ for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
Regs.push_back(Reg);
}
if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
Regs.push_back(Reg);
}
void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
assert(State == NULL);
void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
assert(State == NULL);
- State = new AggressiveAntiDepState(BB);
+ State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
unsigned *KillIndices = State->GetKillIndices();
bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
unsigned *KillIndices = State->GetKillIndices();
DEBUG(errs() << "\tRegs:");
unsigned *DefIndices = State->GetDefIndices();
DEBUG(errs() << "\tRegs:");
unsigned *DefIndices = State->GetDefIndices();
- for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
+ for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
// If Reg is current live, then mark that it can't be renamed as
// we don't know the extent of its live-range anymore (now that it
// has been scheduled). If it is not live but was defined in the
// If Reg is current live, then mark that it can't be renamed as
// we don't know the extent of its live-range anymore (now that it
// has been scheduled). If it is not live but was defined in the
} RegisterReference;
private:
} RegisterReference;
private:
+ /// NumTargetRegs - Number of non-virtual target registers
+ /// (i.e. TRI->getNumRegs()).
+ const unsigned NumTargetRegs;
+
/// GroupNodes - Implements a disjoint-union data structure to
/// form register groups. A node is represented by an index into
/// the vector. A node can "point to" itself to indicate that it
/// GroupNodes - Implements a disjoint-union data structure to
/// form register groups. A node is represented by an index into
/// the vector. A node can "point to" itself to indicate that it
unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
public:
unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
public:
- AggressiveAntiDepState(MachineBasicBlock *BB);
+ AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB);
/// GetKillIndices - Return the kill indices.
unsigned *GetKillIndices() { return KillIndices; }
/// GetKillIndices - Return the kill indices.
unsigned *GetKillIndices() { return KillIndices; }
static_cast<const TargetRegisterClass *>(0));
// Initialize the indices to indicate that no registers are live.
static_cast<const TargetRegisterClass *>(0));
// Initialize the indices to indicate that no registers are live.
- std::fill(KillIndices, array_endof(KillIndices), ~0u);
- std::fill(DefIndices, array_endof(DefIndices), BB->size());
+ const unsigned BBSize = BB->size();
+ for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
+ KillIndices[i] = ~0u;
+ DefIndices[i] = BBSize;
+ }
// Clear "do not change" set.
KeepRegs.clear();
// Clear "do not change" set.
KeepRegs.clear();
// may have been rescheduled and its lifetime may overlap with registers
// in ways not reflected in our current liveness state. For each such
// register, adjust the liveness state to be conservatively correct.
// may have been rescheduled and its lifetime may overlap with registers
// in ways not reflected in our current liveness state. For each such
// register, adjust the liveness state to be conservatively correct.
- for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg)
+ for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
// Mark this register to be non-renamable.
if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
// Mark this register to be non-renamable.
///
void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
// Initialize the indices to indicate that no registers are live.
///
void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
// Initialize the indices to indicate that no registers are live.
- std::fill(KillIndices, array_endof(KillIndices), ~0u);
+ for (unsigned i = 0; i < TRI->getNumRegs(); ++i)
+ KillIndices[i] = ~0u;
// Determine the live-out physregs for this block.
if (!BB->empty() && BB->back().getDesc().isReturn()) {
// Determine the live-out physregs for this block.
if (!BB->empty() && BB->back().getDesc().isReturn()) {