git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876
91177308-0d34-0410-b5e6-
96231b3b80d8
31 files changed:
/// @param address - The address, in the memory space of region, of the first
/// byte of the instruction.
/// @param vStream - The stream to print warnings and diagnostic messages on.
/// @param address - The address, in the memory space of region, of the first
/// byte of the instruction.
/// @param vStream - The stream to print warnings and diagnostic messages on.
+ /// @param cStream - The stream to print comments and annotations on.
/// @return - MCDisassembler::Success if the instruction is valid,
/// MCDisassembler::SoftFail if the instruction was
/// disassemblable but invalid,
/// @return - MCDisassembler::Success if the instruction is valid,
/// MCDisassembler::SoftFail if the instruction was
/// disassemblable but invalid,
uint64_t& size,
const MemoryObject ®ion,
uint64_t address,
uint64_t& size,
const MemoryObject ®ion,
uint64_t address,
- raw_ostream &vStream) const = 0;
+ raw_ostream &vStream,
+ raw_ostream &cStream) const = 0;
/// getEDInfo - Returns the enhanced instruction information corresponding to
/// the disassembler.
/// getEDInfo - Returns the enhanced instruction information corresponding to
/// the disassembler.
class MCInst {
unsigned Opcode;
SmallVector<MCOperand, 8> Operands;
class MCInst {
unsigned Opcode;
SmallVector<MCOperand, 8> Operands;
- SmallVector<std::string, 1> Annotations;
public:
MCInst() : Opcode(0) {}
public:
MCInst() : Opcode(0) {}
Operands.push_back(Op);
}
Operands.push_back(Op);
}
- void addAnnotation(const std::string &Annot) {
- Annotations.push_back(Annot);
- }
-
- void clear() {
- Operands.clear();
- Annotations.clear();
- }
-
+ void clear() { Operands.clear(); }
size_t size() { return Operands.size(); }
typedef SmallVector<MCOperand, 8>::iterator iterator;
size_t size() { return Operands.size(); }
typedef SmallVector<MCOperand, 8>::iterator iterator;
return Operands.insert(I, Op);
}
return Operands.insert(I, Op);
}
- size_t getNumAnnotations() const { return Annotations.size(); }
- std::string getAnnotation(size_t i) const { return Annotations[i]; }
-
void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
void dump() const;
void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
void dump() const;
/// The current set of available features.
unsigned AvailableFeatures;
/// The current set of available features.
unsigned AvailableFeatures;
+
+ /// Utility function for printing annotations.
+ void printAnnotation(raw_ostream &OS, StringRef Annot);
public:
MCInstPrinter(const MCAsmInfo &mai)
: CommentStream(0), MAI(mai), AvailableFeatures(0) {}
public:
MCInstPrinter(const MCAsmInfo &mai)
: CommentStream(0), MAI(mai), AvailableFeatures(0) {}
/// printInst - Print the specified MCInst to the specified raw_ostream.
///
/// printInst - Print the specified MCInst to the specified raw_ostream.
///
- virtual void printInst(const MCInst *MI, raw_ostream &OS) = 0;
-
- /// printAnnotations - Print the annotation comments attached to specified
- /// MCInst to the specified raw_ostream.
- void printAnnotations(const MCInst *MI, raw_ostream &OS);
+ virtual void printInst(const MCInst *MI, raw_ostream &OS,
+ StringRef Annot) = 0;
/// getOpcodeName - Return the name of the specified opcode enum (e.g.
/// "MOV32ri") or empty if we can't resolve it.
/// getOpcodeName - Return the name of the specified opcode enum (e.g.
/// "MOV32ri") or empty if we can't resolve it.
// If we have an AsmPrinter, use that to print, otherwise print the MCInst.
if (InstPrinter)
// If we have an AsmPrinter, use that to print, otherwise print the MCInst.
if (InstPrinter)
- InstPrinter->printInst(&Inst, OS);
+ InstPrinter->printInst(&Inst, OS, "");
else
Inst.print(OS, &MAI);
EmitEOL();
else
Inst.print(OS, &MAI);
EmitEOL();
MCInstPrinter *IP = DC->getIP();
MCDisassembler::DecodeStatus S;
S = DisAsm->getInstruction(Inst, Size, MemoryObject, PC,
MCInstPrinter *IP = DC->getIP();
MCDisassembler::DecodeStatus S;
S = DisAsm->getInstruction(Inst, Size, MemoryObject, PC,
+ /*REMOVE*/ nulls(), DC->CommentStream);
switch (S) {
case MCDisassembler::Fail:
case MCDisassembler::SoftFail:
switch (S) {
case MCDisassembler::Fail:
case MCDisassembler::SoftFail:
return 0;
case MCDisassembler::Success: {
return 0;
case MCDisassembler::Success: {
- SmallVector<char, 64> InsnStr;
- raw_svector_ostream OS(InsnStr);
- IP->printInst(&Inst, OS);
- OS.flush();
-
DC->CommentStream.flush();
DC->CommentStream.flush();
- assert(DC->CommentsToEmit.back() == '\n');
-
- DC->CommentsToEmit.push_back('\n');
StringRef Comments = DC->CommentsToEmit.str();
StringRef Comments = DC->CommentsToEmit.str();
- do {
- // Emit a line of comments.
- size_t Position = Comments.find('\n');
- OS << ' ' << DC->getAsmInfo()->getCommentString()
- << ' ' << Comments.substr(0, Position) << '\n';
-
- Comments = Comments.substr(Position+1);
- } while (!Comments.empty());
+ SmallVector<char, 64> InsnStr;
+ raw_svector_ostream OS(InsnStr);
+ IP->printInst(&Inst, OS, Comments);
+ OS.flush();
- DC->CommentsToEmit.clear();
// Tell the comment stream that the vector changed underneath it.
// Tell the comment stream that the vector changed underneath it.
+ DC->CommentsToEmit.clear();
DC->CommentStream.resync();
assert(OutStringSize != 0 && "Output buffer cannot be zero size");
DC->CommentStream.resync();
assert(OutStringSize != 0 && "Output buffer cannot be zero size");
MCDisassembler::DecodeStatus S;
S = Disassembler->getInstruction(*inst, byteSize, memoryObject, address,
MCDisassembler::DecodeStatus S;
S = Disassembler->getInstruction(*inst, byteSize, memoryObject, address,
switch (S) {
case MCDisassembler::Fail:
case MCDisassembler::SoftFail:
switch (S) {
case MCDisassembler::Fail:
case MCDisassembler::SoftFail:
int EDDisassembler::printInst(std::string &str, MCInst &inst) {
PrinterMutex.acquire();
int EDDisassembler::printInst(std::string &str, MCInst &inst) {
PrinterMutex.acquire();
- InstPrinter->printInst(&inst, *InstStream);
+ InstPrinter->printInst(&inst, *InstStream, "");
InstStream->flush();
str = *InstString;
InstString->clear();
InstStream->flush();
str = *InstString;
InstString->clear();
OS << " ";
getOperand(i).print(OS, MAI);
}
OS << " ";
getOperand(i).print(OS, MAI);
}
-
- if (getNumAnnotations()) {
- OS << " # Annots: ";
- for (unsigned i = 0, e = getNumAnnotations(); i != e; ++i) {
- OS << " \"";
- OS << getAnnotation(i);
- OS << '"';
- }
- }
-
OS << Separator;
getOperand(i).print(OS, MAI);
}
OS << Separator;
getOperand(i).print(OS, MAI);
}
-
- if (getNumAnnotations()) {
- OS << " # Annots: ";
- for (unsigned i = 0, e = getNumAnnotations(); i != e; ++i) {
- OS << Separator;
- OS << '"';
- OS << getAnnotation(i);
- OS << '"';
- }
- }
-
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCInstPrinter.h"
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCInstPrinter.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCInst.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
assert(0 && "Target should implement this");
}
assert(0 && "Target should implement this");
}
-void MCInstPrinter::printAnnotations(const MCInst *MI, raw_ostream &OS) {
- for (unsigned i = 0, e = MI->getNumAnnotations(); i != e; ++i) {
- OS << MI->getAnnotation(i) << "\n";
- }
+void MCInstPrinter::printAnnotation(raw_ostream &OS, StringRef Annot) {
+ if (!Annot.empty()) OS << Annot << "\n";
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
- raw_ostream &vStream) const;
+ raw_ostream &vStream,
+ raw_ostream &cStream) const;
/// getEDInfo - See MCDisassembler.
EDInstInfo *getEDInfo() const;
/// getEDInfo - See MCDisassembler.
EDInstInfo *getEDInfo() const;
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
- raw_ostream &vStream) const;
+ raw_ostream &vStream,
+ raw_ostream &cStream) const;
/// getEDInfo - See MCDisassembler.
EDInstInfo *getEDInfo() const;
/// getEDInfo - See MCDisassembler.
EDInstInfo *getEDInfo() const;
DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
const MemoryObject &Region,
uint64_t Address,
DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
const MemoryObject &Region,
uint64_t Address,
- raw_ostream &os) const {
+ raw_ostream &os,
+ raw_ostream &cs) const {
uint8_t bytes[4];
assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
uint8_t bytes[4];
assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
const MemoryObject &Region,
uint64_t Address,
DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
const MemoryObject &Region,
uint64_t Address,
- raw_ostream &os) const {
+ raw_ostream &os,
+ raw_ostream &cs) const {
uint8_t bytes[4];
assert((STI.getFeatureBits() & ARM::ModeThumb) &&
uint8_t bytes[4];
assert((STI.getFeatureBits() & ARM::ModeThumb) &&
OS << getRegisterName(RegNo);
}
OS << getRegisterName(RegNo);
}
-void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
+void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
+ StringRef Annot) {
unsigned Opcode = MI->getOpcode();
// Check for MOVs and print canonical forms, instead.
unsigned Opcode = MI->getOpcode();
// Check for MOVs and print canonical forms, instead.
O << ", " << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
O << ", " << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
-
- if (CommentStream) printAnnotations(MI, *CommentStream);
-
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
<< ", " << getRegisterName(MO1.getReg());
if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
<< ", " << getRegisterName(MO1.getReg());
if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
return;
}
O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
return;
}
O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
-
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
return;
}
if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
return;
}
if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
O << '\t' << "push";
printPredicateOperand(MI, 4, O);
O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
O << '\t' << "push";
printPredicateOperand(MI, 4, O);
O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
return;
}
if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
return;
}
if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
O << '\t' << "pop";
printPredicateOperand(MI, 5, O);
O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
O << '\t' << "pop";
printPredicateOperand(MI, 5, O);
O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
if (Writeback) O << "!";
O << ", ";
printRegisterList(MI, 3, O);
if (Writeback) O << "!";
O << ", ";
printRegisterList(MI, 3, O);
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
MI->getOperand(1).getReg() == ARM::R8) {
O << "\tnop";
printPredicateOperand(MI, 2, O);
MI->getOperand(1).getReg() == ARM::R8) {
O << "\tnop";
printPredicateOperand(MI, 2, O);
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
return;
}
printInstruction(MI, O);
return;
}
printInstruction(MI, O);
- if (CommentStream) printAnnotations(MI, *CommentStream);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
}
void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
public:
ARMInstPrinter(const MCAsmInfo &MAI, const MCSubtargetInfo &STI);
public:
ARMInstPrinter(const MCAsmInfo &MAI, const MCSubtargetInfo &STI);
- virtual void printInst(const MCInst *MI, raw_ostream &O);
+ virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const;
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual StringRef getOpcodeName(unsigned Opcode) const;
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
- raw_ostream &vStream) const {
+ raw_ostream &vStream,
+ raw_ostream &cStream) const {
// The machine instruction.
uint32_t insn;
uint64_t read;
// The machine instruction.
uint32_t insn;
uint64_t read;
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
- raw_ostream &vStream) const;
+ raw_ostream &vStream,
+ raw_ostream &cStream) const;
/// getEDInfo - See MCDisassembler.
EDInstInfo *getEDInfo() const;
/// getEDInfo - See MCDisassembler.
EDInstInfo *getEDInfo() const;
// Include the auto-generated portion of the assembly writer.
#include "MBlazeGenAsmWriter.inc"
// Include the auto-generated portion of the assembly writer.
#include "MBlazeGenAsmWriter.inc"
-void MBlazeInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
+void MBlazeInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
+ StringRef Annot) {
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
}
void MBlazeInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
void MBlazeInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
MBlazeInstPrinter(const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {}
MBlazeInstPrinter(const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {}
- virtual void printInst(const MCInst *MI, raw_ostream &O);
+ virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
// Include the auto-generated portion of the assembly writer.
#include "MSP430GenAsmWriter.inc"
// Include the auto-generated portion of the assembly writer.
#include "MSP430GenAsmWriter.inc"
-void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
+void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
+ StringRef Annot) {
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
}
void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo,
}
void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo,
MSP430InstPrinter(const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {}
MSP430InstPrinter(const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {}
- virtual void printInst(const MCInst *MI, raw_ostream &O);
+ virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
OS << '$' << LowercaseString(getRegisterName(RegNo));
}
OS << '$' << LowercaseString(getRegisterName(RegNo));
}
-void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
+void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
+ StringRef Annot) {
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
}
void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
virtual StringRef getOpcodeName(unsigned Opcode) const;
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual StringRef getOpcodeName(unsigned Opcode) const;
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
- virtual void printInst(const MCInst *MI, raw_ostream &O);
+ virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
private:
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
private:
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
// If we have an AsmPrinter, use that to print, otherwise print the MCInst.
if (InstPrinter)
// If we have an AsmPrinter, use that to print, otherwise print the MCInst.
if (InstPrinter)
- InstPrinter->printInst(&Inst, OS);
+ InstPrinter->printInst(&Inst, OS, "");
else
Inst.print(OS, &MAI);
EmitEOL();
else
Inst.print(OS, &MAI);
EmitEOL();
OS << getRegisterName(RegNo);
}
OS << getRegisterName(RegNo);
}
-void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
+void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
+ StringRef Annot) {
// Check for slwi/srwi mnemonics.
if (MI->getOpcode() == PPC::RLWINM) {
unsigned char SH = MI->getOperand(2).getImm();
// Check for slwi/srwi mnemonics.
if (MI->getOpcode() == PPC::RLWINM) {
unsigned char SH = MI->getOperand(2).getImm();
O << ", ";
printOperand(MI, 1, O);
O << ", " << (unsigned int)SH;
O << ", ";
printOperand(MI, 1, O);
O << ", " << (unsigned int)SH;
+
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
printOperand(MI, 0, O);
O << ", ";
printOperand(MI, 1, O);
printOperand(MI, 0, O);
O << ", ";
printOperand(MI, 1, O);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
O << ", ";
printOperand(MI, 1, O);
O << ", " << (unsigned int)SH;
O << ", ";
printOperand(MI, 1, O);
O << ", " << (unsigned int)SH;
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
return;
}
}
printInstruction(MI, O);
return;
}
}
printInstruction(MI, O);
+ if (CommentStream) printAnnotation(*CommentStream, Annot);
}
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
}
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
- virtual void printInst(const MCInst *MI, raw_ostream &O);
+ virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const;
static const char *getInstructionName(unsigned Opcode);
virtual StringRef getOpcodeName(unsigned Opcode) const;
static const char *getInstructionName(unsigned Opcode);
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
- raw_ostream &vStream) const {
+ raw_ostream &vStream,
+ raw_ostream &cStream) const {
InternalInstruction internalInstr;
int ret = decodeInstruction(&internalInstr,
InternalInstruction internalInstr;
int ret = decodeInstruction(&internalInstr,
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
- raw_ostream &vStream) const;
+ raw_ostream &vStream,
+ raw_ostream &cStream) const;
/// getEDInfo - See MCDisassembler.
EDInstInfo *getEDInfo() const;
/// getEDInfo - See MCDisassembler.
EDInstInfo *getEDInfo() const;
OS << '%' << getRegisterName(RegNo);
}
OS << '%' << getRegisterName(RegNo);
}
-void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
+void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
+ StringRef Annot) {
// Try to print any aliases first.
if (!printAliasInstr(MI, OS))
printInstruction(MI, OS);
// If verbose assembly is enabled, we can print some informative comments.
if (CommentStream) {
// Try to print any aliases first.
if (!printAliasInstr(MI, OS))
printInstruction(MI, OS);
// If verbose assembly is enabled, we can print some informative comments.
if (CommentStream) {
- printAnnotations(MI, *CommentStream);
+ printAnnotation(*CommentStream, Annot);
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
}
}
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
}
}
X86ATTInstPrinter(const MCAsmInfo &MAI);
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
X86ATTInstPrinter(const MCAsmInfo &MAI);
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
- virtual void printInst(const MCInst *MI, raw_ostream &OS);
+ virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const;
// Autogenerated by tblgen, returns true if we successfully printed an
virtual StringRef getOpcodeName(unsigned Opcode) const;
// Autogenerated by tblgen, returns true if we successfully printed an
OS << getRegisterName(RegNo);
}
OS << getRegisterName(RegNo);
}
-void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
+void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
+ StringRef Annot) {
printInstruction(MI, OS);
// If verbose assembly is enabled, we can print some informative comments.
if (CommentStream) {
printInstruction(MI, OS);
// If verbose assembly is enabled, we can print some informative comments.
if (CommentStream) {
- printAnnotations(MI, *CommentStream);
+ printAnnotation(*CommentStream, Annot);
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
}
}
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
}
}
: MCInstPrinter(MAI) {}
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
: MCInstPrinter(MAI) {}
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
- virtual void printInst(const MCInst *MI, raw_ostream &OS);
+ virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const;
// Autogenerated by tblgen.
virtual StringRef getOpcodeName(unsigned Opcode) const;
// Autogenerated by tblgen.
MCDisassembler::DecodeStatus S;
S = DisAsm.getInstruction(Inst, Size, memoryObject, Index,
MCDisassembler::DecodeStatus S;
S = DisAsm.getInstruction(Inst, Size, memoryObject, Index,
+ /*REMOVE*/ nulls(), nulls());
switch (S) {
case MCDisassembler::Fail:
SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second),
switch (S) {
case MCDisassembler::Fail:
SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second),
// Fall through
case MCDisassembler::Success:
// Fall through
case MCDisassembler::Success:
- Printer.printInst(&Inst, Out);
+ Printer.printInst(&Inst, Out, "");
for (uint64_t Index = Start; Index < End; Index += Size) {
MCInst Inst;
for (uint64_t Index = Start; Index < End; Index += Size) {
MCInst Inst;
- if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut)) {
+ if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut, nulls())) {
if (Ana->isBranch(Inst)) {
uint64_t targ = Ana->evaluateBranch(Inst, Index, Size);
// FIXME: Distinguish relocations from nop jumps.
if (Ana->isBranch(Inst)) {
uint64_t targ = Ana->evaluateBranch(Inst, Index, Size);
// FIXME: Distinguish relocations from nop jumps.
if (!CFG) {
for (Index = Start; Index < End; Index += Size) {
MCInst Inst;
if (!CFG) {
for (Index = Start; Index < End; Index += Size) {
MCInst Inst;
if (DisAsm->getInstruction(Inst, Size, memoryObject, Index,
if (DisAsm->getInstruction(Inst, Size, memoryObject, Index,
uint64_t addr;
if (error(i->getAddress(addr))) break;
outs() << format("%8x:\t", addr + Index);
DumpBytes(StringRef(Bytes.data() + Index, Size));
uint64_t addr;
if (error(i->getAddress(addr))) break;
outs() << format("%8x:\t", addr + Index);
DumpBytes(StringRef(Bytes.data() + Index, Size));
- IP->printInst(&Inst, outs());
+ IP->printInst(&Inst, outs(), "");
outs() << "\n";
} else {
errs() << ToolName << ": warning: invalid instruction encoding\n";
outs() << "\n";
} else {
errs() << ToolName << ": warning: invalid instruction encoding\n";
// Simple loops.
if (fi->second.contains(&fi->second))
outs() << '\t';
// Simple loops.
if (fi->second.contains(&fi->second))
outs() << '\t';
- IP->printInst(&Inst.Inst, outs());
+ IP->printInst(&Inst.Inst, outs(), "");
// Escape special chars and print the instruction in mnemonic form.
std::string Str;
raw_string_ostream OS(Str);
// Escape special chars and print the instruction in mnemonic form.
std::string Str;
raw_string_ostream OS(Str);
- IP->printInst(&i->second.getInsts()[ii].Inst, OS);
+ IP->printInst(&i->second.getInsts()[ii].Inst, OS, "");
Out << DOT::EscapeString(OS.str()) << '|';
}
Out << "<o>\" shape=\"record\" ];\n";
Out << DOT::EscapeString(OS.str()) << '|';
}
Out << "<o>\" shape=\"record\" ];\n";