but SYNC with an implied operand ($stype = 0) is valid since Mips2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211185
91177308-0d34-0410-b5e6-
96231b3b80d8
18 files changed:
ISA_MIPS1_NOT_32R6_64R6;
}
ISA_MIPS1_NOT_32R6_64R6;
}
-def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
+def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
(SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"srl $rd, $rt, $rs",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
(SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"srl $rd, $rt, $rs",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"sync",
+ (SYNC 0), 1>, ISA_MIPS2;
//===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//
(ADDiu GPR32:$src, imm:$imm)>;
}
(ADDiu GPR32:$src, imm:$imm)>;
}
+// SYNC
+def : MipsPat<(MipsSync (i32 immz)),
+ (SYNC 0)>, ISA_MIPS2;
+
// Call
def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
(JAL tglobaladdr:$dst)>;
// Call
def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
(JAL tglobaladdr:$dst)>;
; ALL: ll
; ALL: sc
; ALL: beq
; ALL: ll
; ALL: sc
; ALL: beq
}
; make sure that this assertion in
}
; make sure that this assertion in
tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
--- /dev/null
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swc3 $10,-32265($k0)
swl $15,13694($s3)
swr $s1,-26590($14)
swc3 $10,-32265($k0)
swl $15,13694($s3)
swr $s1,-26590($14)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
--- /dev/null
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3)
swr $s1,-26590($14)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3)
swr $s1,-26590($14)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3)
swr $s1,-26590($14)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3)
swr $s1,-26590($14)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
--- /dev/null
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
--- /dev/null
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips5 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]