opcode and operand with a tab. Check for these instructions in the usual
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411
91177308-0d34-0410-b5e6-
96231b3b80d8
// ...likewise if it ends with a branch table followed by an unconditional
// branch. The branch folder can create these, and we must get rid of them for
// correctness of Thumb constant islands.
// ...likewise if it ends with a branch table followed by an unconditional
// branch. The branch folder can create these, and we must get rid of them for
// correctness of Thumb constant islands.
- if (isJumpTableBranchOpcode(SecondLastOpc) &&
+ if ((isJumpTableBranchOpcode(SecondLastOpc) ||
+ isIndirectBranchOpcode(SecondLastOpc)) &&
isUncondBranchOpcode(LastOpc)) {
I = LastInst;
if (AllowModify)
isUncondBranchOpcode(LastOpc)) {
I = LastInst;
if (AllowModify)
Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
}
Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
}
+static inline
+bool isIndirectBranchOpcode(int Opc) {
+ return Opc == ARM::BRIND || Opc == ARM::tBRIND;
+}
+
/// getInstrPredicate - If instruction is predicated, returns its predicate
/// condition, otherwise returns AL. It also returns the condition code
/// register by reference.
/// getInstrPredicate - If instruction is predicated, returns its predicate
/// condition, otherwise returns AL. It also returns the condition code
/// register by reference.
case ARM::BX_RET: // Return.
case ARM::LDM_RET:
case ARM::B:
case ARM::BX_RET: // Return.
case ARM::LDM_RET:
case ARM::B:
case ARM::BR_JTr: // Jumptable branch.
case ARM::BR_JTm: // Jumptable branch through mem.
case ARM::BR_JTadd: // Jumptable branch add to pc.
case ARM::BR_JTr: // Jumptable branch.
case ARM::BR_JTm: // Jumptable branch through mem.
case ARM::BR_JTadd: // Jumptable branch add to pc.
// Indirect branches
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
// Indirect branches
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
- def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx $dst",
+ def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
[(brind GPR:$dst)]> {
let Inst{7-4} = 0b0001;
let Inst{19-8} = 0b111111111111;
[(brind GPR:$dst)]> {
let Inst{7-4} = 0b0001;
let Inst{19-8} = 0b111111111111;
def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>;
}
def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>;
}
+// Indirect branches
+let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
+ def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "bx\t$dst",
+ [(brind GPR:$dst)]>;
+}
+
// FIXME: remove when we have a way to marking a MI with these properties.
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1 in
// FIXME: remove when we have a way to marking a MI with these properties.
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1 in
case ARM::tBX_RET_vararg:
case ARM::tPOP_RET:
case ARM::tB:
case ARM::tBX_RET_vararg:
case ARM::tPOP_RET:
case ARM::tB:
case ARM::tBR_JTr:
return true;
default:
case ARM::tBR_JTr:
return true;
default:
case ARM::tBX_RET_vararg:
case ARM::tPOP_RET:
case ARM::tB:
case ARM::tBX_RET_vararg:
case ARM::tPOP_RET:
case ARM::tB:
return true;
default:
break;
return true;
default:
break;