+// List of CPU names and their arches.
+// The same CPU can have multiple arches and can be default on multiple arches.
+// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
+// FIXME: TableGen this.
+struct {
+ const char *Name;
+ ARM::ArchKind ArchID;
+ bool Default;
+} CPUNames[] = {
+ { "arm2", ARM::AK_ARMV2, true },
+ { "arm6", ARM::AK_ARMV3, true },
+ { "arm7m", ARM::AK_ARMV3M, true },
+ { "strongarm", ARM::AK_ARMV4, true },
+ { "arm7tdmi", ARM::AK_ARMV4T, true },
+ { "arm7tdmi-s", ARM::AK_ARMV4T, false },
+ { "arm710t", ARM::AK_ARMV4T, false },
+ { "arm720t", ARM::AK_ARMV4T, false },
+ { "arm9", ARM::AK_ARMV4T, false },
+ { "arm9tdmi", ARM::AK_ARMV4T, false },
+ { "arm920", ARM::AK_ARMV4T, false },
+ { "arm920t", ARM::AK_ARMV4T, false },
+ { "arm922t", ARM::AK_ARMV4T, false },
+ { "arm9312", ARM::AK_ARMV4T, false },
+ { "arm940t", ARM::AK_ARMV4T, false },
+ { "ep9312", ARM::AK_ARMV4T, false },
+ { "arm10tdmi", ARM::AK_ARMV5, true },
+ { "arm10tdmi", ARM::AK_ARMV5T, true },
+ { "arm1020t", ARM::AK_ARMV5T, false },
+ { "xscale", ARM::AK_XSCALE, true },
+ { "xscale", ARM::AK_ARMV5TE, false },
+ { "arm9e", ARM::AK_ARMV5TE, false },
+ { "arm926ej-s", ARM::AK_ARMV5TE, false },
+ { "arm946ej-s", ARM::AK_ARMV5TE, false },
+ { "arm966e-s", ARM::AK_ARMV5TE, false },
+ { "arm968e-s", ARM::AK_ARMV5TE, false },
+ { "arm1020e", ARM::AK_ARMV5TE, false },
+ { "arm1022e", ARM::AK_ARMV5TE, true },
+ { "iwmmxt", ARM::AK_ARMV5TE, false },
+ { "iwmmxt", ARM::AK_IWMMXT, true },
+ { "arm1136jf-s", ARM::AK_ARMV6, true },
+ { "arm1136j-s", ARM::AK_ARMV6J, true },
+ { "arm1136jz-s", ARM::AK_ARMV6J, false },
+ { "arm1176j-s", ARM::AK_ARMV6K, false },
+ { "mpcore", ARM::AK_ARMV6K, false },
+ { "mpcorenovfp", ARM::AK_ARMV6K, false },
+ { "arm1176jzf-s", ARM::AK_ARMV6K, true },
+ { "arm1176jzf-s", ARM::AK_ARMV6Z, true },
+ { "arm1176jzf-s", ARM::AK_ARMV6ZK, true },
+ { "arm1156t2-s", ARM::AK_ARMV6T2, true },
+ { "arm1156t2f-s", ARM::AK_ARMV6T2, false },
+ { "cortex-m0", ARM::AK_ARMV6M, true },
+ { "cortex-m0plus", ARM::AK_ARMV6M, false },
+ { "cortex-m1", ARM::AK_ARMV6M, false },
+ { "sc000", ARM::AK_ARMV6M, false },
+ { "cortex-a8", ARM::AK_ARMV7, true },
+ { "cortex-a5", ARM::AK_ARMV7A, false },
+ { "cortex-a7", ARM::AK_ARMV7A, false },
+ { "cortex-a8", ARM::AK_ARMV7A, true },
+ { "cortex-a9", ARM::AK_ARMV7A, false },
+ { "cortex-a12", ARM::AK_ARMV7A, false },
+ { "cortex-a15", ARM::AK_ARMV7A, false },
+ { "cortex-a17", ARM::AK_ARMV7A, false },
+ { "krait", ARM::AK_ARMV7A, false },
+ { "cortex-r4", ARM::AK_ARMV7R, true },
+ { "cortex-r4f", ARM::AK_ARMV7R, false },
+ { "cortex-r5", ARM::AK_ARMV7R, false },
+ { "cortex-r7", ARM::AK_ARMV7R, false },
+ { "sc300", ARM::AK_ARMV7M, false },
+ { "cortex-m3", ARM::AK_ARMV7M, true },
+ { "cortex-m4", ARM::AK_ARMV7M, false },
+ { "cortex-m7", ARM::AK_ARMV7M, false },
+ { "cortex-a53", ARM::AK_ARMV8A, true },
+ { "cortex-a57", ARM::AK_ARMV8A, false },
+ { "cortex-a72", ARM::AK_ARMV8A, false },
+ { "cyclone", ARM::AK_ARMV8A, false },
+ { "generic", ARM::AK_ARMV8_1A, true },
+ // Non-standard Arch names.
+ { "arm1022e", ARM::AK_ARMV5E, true },
+ { "arm926ej-s", ARM::AK_ARMV5TEJ, true },
+ { "cortex-m0", ARM::AK_ARMV6SM, true },
+ { "cortex-a8", ARM::AK_ARMV7L, true },
+ { "cortex-m4", ARM::AK_ARMV7EM, true },
+ { "swift", ARM::AK_ARMV7S, true },
+ // Invalid CPU
+ { "invalid", ARM::AK_INVALID, true }
+};